1. 20 1月, 2009 1 次提交
    • T
      x86: cleanup stack protector · c6e50f93
      Tejun Heo 提交于
      Impact: cleanup
      
      Make the following cleanups.
      
      * remove duplicate comment from boot_init_stack_canary() which fits
        better in the other place - cpu_idle().
      
      * move stack_canary offset check from __switch_to() to
        boot_init_stack_canary().
      Signed-off-by: NTejun Heo <tj@kernel.org>
      c6e50f93
  2. 18 1月, 2009 10 次提交
  3. 16 1月, 2009 6 次提交
    • I
      percpu: add optimized generic percpu accessors · 6dbde353
      Ingo Molnar 提交于
      It is an optimization and a cleanup, and adds the following new
      generic percpu methods:
      
        percpu_read()
        percpu_write()
        percpu_add()
        percpu_sub()
        percpu_and()
        percpu_or()
        percpu_xor()
      
      and implements support for them on x86. (other architectures will fall
      back to a default implementation)
      
      The advantage is that for example to read a local percpu variable,
      instead of this sequence:
      
       return __get_cpu_var(var);
      
       ffffffff8102ca2b:	48 8b 14 fd 80 09 74 	mov    -0x7e8bf680(,%rdi,8),%rdx
       ffffffff8102ca32:	81
       ffffffff8102ca33:	48 c7 c0 d8 59 00 00 	mov    $0x59d8,%rax
       ffffffff8102ca3a:	48 8b 04 10          	mov    (%rax,%rdx,1),%rax
      
      We can get a single instruction by using the optimized variants:
      
       return percpu_read(var);
      
       ffffffff8102ca3f:	65 48 8b 05 91 8f fd 	mov    %gs:0x7efd8f91(%rip),%rax
      
      I also cleaned up the x86-specific APIs and made the x86 code use
      these new generic percpu primitives.
      
      tj: * fixed generic percpu_sub() definition as Roel Kluin pointed out
          * added percpu_and() for completeness's sake
          * made generic percpu ops atomic against preemption
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      6dbde353
    • T
      x86: convert pda ops to wrappers around x86 percpu accessors · 49357d19
      Tejun Heo 提交于
      pda is now a percpu variable and there's no reason it can't use plain
      x86 percpu accessors.  Add x86_test_and_clear_bit_percpu() and replace
      pda op implementations with wrappers around x86 percpu accessors.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      49357d19
    • T
      x86: make pda a percpu variable · b12d8db8
      Tejun Heo 提交于
      [ Based on original patch from Christoph Lameter and Mike Travis. ]
      
      As pda is now allocated in percpu area, it can easily be made a proper
      percpu variable.  Make it so by defining per cpu symbol from linker
      script and declaring it in C code for SMP and simply defining it for
      UP.  This change cleans up code and brings SMP and UP closer a bit.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      b12d8db8
    • T
      x86: merge 64 and 32 SMP percpu handling · 9939ddaf
      Tejun Heo 提交于
      Now that pda is allocated as part of percpu, percpu doesn't need to be
      accessed through pda.  Unify x86_64 SMP percpu access with x86_32 SMP
      one.  Other than the segment register, operand size and the base of
      percpu symbols, they behave identical now.
      
      This patch replaces now unnecessary pda->data_offset with a dummy
      field which is necessary to keep stack_canary at its place.  This
      patch also moves per_cpu_offset initialization out of init_gdt() into
      setup_per_cpu_areas().  Note that this change also necessitates
      explicit per_cpu_offset initializations in voyager_smp.c.
      
      With this change, x86_OP_percpu()'s are as efficient on x86_64 as on
      x86_32 and also x86_64 can use assembly PER_CPU macros.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      9939ddaf
    • T
      x86: use static _cpu_pda array · c8f3329a
      Tejun Heo 提交于
      _cpu_pda array first uses statically allocated storage in data.init
      and then switches to allocated bootmem to conserve space.  However,
      after folding pda area into percpu area, _cpu_pda array will be
      removed completely.  Drop the reallocation part to simplify the code
      for soon-to-follow changes.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c8f3329a
    • T
      x86: fix pda_to_op() · 7de6883f
      Tejun Heo 提交于
      There's no instruction to move a 64bit immediate into memory location.
      Drop "i".
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      7de6883f
  4. 23 10月, 2008 2 次提交
  5. 23 7月, 2008 1 次提交
    • V
      x86: consolidate header guards · 77ef50a5
      Vegard Nossum 提交于
      This patch is the result of an automatic script that consolidates the
      format of all the headers in include/asm-x86/.
      
      The format:
      
      1. No leading underscore. Names with leading underscores are reserved.
      2. Pathname components are separated by two underscores. So we can
         distinguish between mm_types.h and mm/types.h.
      3. Everything except letters and numbers are turned into single
         underscores.
      Signed-off-by: NVegard Nossum <vegard.nossum@gmail.com>
      77ef50a5
  6. 14 7月, 2008 1 次提交
  7. 08 7月, 2008 2 次提交
  8. 26 5月, 2008 1 次提交
    • I
      x86: fix stackprotector canary updates during context switches · e0032087
      Ingo Molnar 提交于
      fix a bug noticed and fixed by pageexec@freemail.hu.
      
      if built with -fstack-protector-all then we'll have canary checks built
      into the __switch_to() function. That does not work well with the
      canary-switching code there: while we already use the %rsp of the
      new task, we still call __switch_to() whith the previous task's canary
      value in the PDA, hence the __switch_to() ssp prologue instructions
      will store the previous canary. Then we update the PDA and upon return
      from __switch_to() the canary check triggers and we panic.
      
      so update the canary after we have called __switch_to(), where we are
      at the same stackframe level as the last stackframe of the next
      (and now freshly current) task.
      
      Note: this means that we call __switch_to() [and its sub-functions]
      still with the old canary, but that is not a problem, both the previous
      and the next task has a high-quality canary. The only (mostly academic)
      disadvantage is that the canary of one task may leak onto the stack of
      another task, increasing the risk of information leaks, were an attacker
      able to read the stack of specific tasks (but not that of others).
      
      To solve this we'll have to reorganize the way we switch tasks, and move
      the PDA setting into the switch_to() assembly code. That will happen in
      another patch.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      e0032087
  9. 17 4月, 2008 2 次提交
  10. 30 1月, 2008 3 次提交
  11. 18 10月, 2007 1 次提交
    • J
      x86: expand /proc/interrupts to include missing vectors, v2 · 38e760a1
      Joe Korty 提交于
      Add missing IRQs and IRQ descriptions to /proc/interrupts.
      
      /proc/interrupts is most useful when it displays every IRQ vector in use by
      the system, not just those somebody thought would be interesting.
      
      This patch inserts the following vector displays to the i386 and x86_64
      platforms, as appropriate:
      
      	rescheduling interrupts
      	TLB flush interrupts
      	function call interrupts
      	thermal event interrupts
      	threshold interrupts
      	spurious interrupts
      
      A threshold interrupt occurs when ECC memory correction is occuring at too
      high a frequency.  Thresholds are used by the ECC hardware as occasional
      ECC failures are part of normal operation, but long sequences of ECC
      failures usually indicate a memory chip that is about to fail.
      
      Thermal event interrupts occur when a temperature threshold has been
      exceeded for some CPU chip.  IIRC, a thermal interrupt is also generated
      when the temperature drops back to a normal level.
      
      A spurious interrupt is an interrupt that was raised then lowered by the
      device before it could be fully processed by the APIC.  Hence the apic sees
      the interrupt but does not know what device it came from.  For this case
      the APIC hardware will assume a vector of 0xff.
      
      Rescheduling, call, and TLB flush interrupts are sent from one CPU to
      another per the needs of the OS.  Typically, their statistics would be used
      to discover if an interrupt flood of the given type has been occuring.
      
      AK: merged v2 and v4 which had some more tweaks
      AK: replace Local interrupts with Local timer interrupts
      AK: Fixed description of interrupt types.
      
      [ tglx: arch/x86 adaptation ]
      [ mingo: small cleanup ]
      Signed-off-by: NJoe Korty <joe.korty@ccur.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Cc: Tim Hockin <thockin@hockin.org>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      38e760a1
  12. 13 10月, 2007 1 次提交
    • T
      x86: Fix irq0 / local apic timer accounting · 4e77ae3e
      Thomas Gleixner 提交于
      The clock events merge introduced a change to the nmi watchdog code to
      handle the not longer increasing local apic timer count in the
      broadcast mode. This is fine for UP, but on SMP it pampers over a
      stuck CPU which is not handling the broadcast interrupt due to the
      unconditional sum up of local apic timer count and irq0 count.
      
      To cover all cases we need to keep track on which CPU irq0 is
      handled. In theory this is CPU#0 due to the explicit disabling of irq
      balancing for irq0, but there are systems which ignore this on the
      hardware level. The per cpu irq0 accounting allows us to remove the
      irq0 to CPU0 binding as well.
      
      Add a per cpu counter for irq0 and evaluate this instead of the global
      irq0 count in the nmi watchdog code.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NArjan van de Ven <arjan@linux.intel.com>
      4e77ae3e
  13. 11 10月, 2007 1 次提交
  14. 14 11月, 2006 1 次提交
    • A
      [PATCH] x86-64: Fix race in exit_idle · 9446868b
      Andi Kleen 提交于
      When another interrupt happens in exit_idle the exit idle notifier
      could be called an incorrect number of times.
      
      Add a test_and_clear_bit_pda and use it handle the bit
      atomically against interrupts to avoid this.
      
      Pointed out by Stephane Eranian
      Signed-off-by: NAndi Kleen <ak@suse.de>
      9446868b
  15. 26 9月, 2006 7 次提交