1. 05 12月, 2008 22 次提交
  2. 04 12月, 2008 2 次提交
    • J
      sparc64: Fix VIS emulation bugs · 726c12f5
      Joseph Myers 提交于
      This patch fixes some bugs in VIS emulation that cause the GCC test
      failure
      
      FAIL: gcc.target/sparc/pdist-3.c execution test
      
      for both 32-bit and 64-bit testing on hardware lacking these
      instructions.  The emulation code for the pdist instruction uses
      RS1(insn) for both source registers rs1 and rs2, which is obviously
      wrong and leads to the instruction doing nothing (the observed
      problem), and further inspection of the code shows that RS1 uses a
      shift of 24 and RD a shift of 25, which clearly cannot both be right;
      examining SPARC documentation indicates the correct shift for RS1 is
      14.
      
      This patch fixes the bug if single-stepping over the affected
      instruction in the debugger, but not if the testcase is run
      standalone.  For that, Wind River has another patch I hope they will
      send as a followup to this patch submission.
      Signed-off-by: NJoseph Myers <joseph@codesourcery.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      726c12f5
    • R
      sparc: asm/bitops.h should define __fls · e8e8e80e
      Rusty Russell 提交于
      bitops_64.h includes the generic one; pretty sure 32 should too.
      
      (Found by using __fls in generic code and breaking sparc defconfig build:
       thanks Stephen and linux-next!)
      Signed-off-by: NRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e8e8e80e
  3. 03 12月, 2008 6 次提交
  4. 02 12月, 2008 2 次提交
  5. 01 12月, 2008 8 次提交
    • L
      Revert "of_platform_driver noise on sparce" · 33b07db9
      Linus Torvalds 提交于
      This reverts commit e669dae6, since it
      is incomplete, and clashes with fuller patches and the sparc 32/64
      unification effort.
      Requested-by: NDavid Miller <davem@davemloft.net>
      Acked-by: NAl Viro <viro@ZenIV.linux.org.uk>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      33b07db9
    • D
      sparc64: Fix offset calculation in compute_size() · b270ee8a
      David S. Miller 提交于
      The fault address is somewhere inside of the buffer, not
      before it.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b270ee8a
    • M
      powerpc: Fix build for 32-bit SMP configs · a1e0eb10
      Milton Miller 提交于
      attr_smt_snooze_delay is only defined for CONFIG_PPC64, so protect the
      attribute removal with the same condition.  This fixes this build error
      on 32-bit SMP configurations:
      
      /data/home/miltonm/next.git/arch/powerpc/kernel/sysfs.c: In function ‘unregister_cpu_online’:
      /data/home/miltonm/next.git/arch/powerpc/kernel/sysfs.c:722: error: ‘attr_smt_snooze_delay’ undeclared (first use in this function)
      /data/home/miltonm/next.git/arch/powerpc/kernel/sysfs.c:722: error: (Each undeclared identifier is reported only once
      /data/home/miltonm/next.git/arch/powerpc/kernel/sysfs.c:722: error: for each function it appears in.)
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      a1e0eb10
    • P
      powerpc: Fix system calls on Cell entered with XER.SO=1 · ab598b66
      Paul Mackerras 提交于
      It turns out that on Cell, on a kernel with CONFIG_VIRT_CPU_ACCOUNTING
      = y, if a program sets the SO (summary overflow) bit in the XER and
      then does a system call, the SO bit in CR0 will be set on return
      regardless of whether the system call detected an error.  Since CR0.SO
      is used as the error indication from the system call, this means that
      all system calls appear to fail.
      
      The reason is that the workaround for the timebase bug on Cell uses a
      compare instruction.  With CONFIG_VIRT_CPU_ACCOUNTING = y, the
      ACCOUNT_CPU_USER_ENTRY macro reads the timebase, so we end up doing a
      compare instruction, which copies XER.SO to CR0.SO.  Since we were
      doing this in the system call entry patch after clearing CR0.SO but
      before saving the CR, this meant that the saved CR image had CR0.SO
      set if XER.SO was set on entry.
      
      This fixes it by moving the clearing of CR0.SO to after the
      ACCOUNT_CPU_USER_ENTRY call in the system call entry path.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ab598b66
    • A
      powerpc/cell: Fix GDB watchpoints, again · 960cedb4
      Arnd Bergmann 提交于
      An earlier patch from Jens Osterkamp attempted to fix GDB
      watchpoints by enabling the DABRX register at boot time.
      Unfortunately, this did not work on SMP setups, where
      secondary CPUs were still using the power-on DABRX value.
      
      This introduces the same change for secondary CPUs on cell
      as well.
      Reported-by: NUlrich Weigand <Ulrich.Weigand@de.ibm.com>
      Tested-by: NUlrich Weigand <Ulrich.Weigand@de.ibm.com>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      960cedb4
    • A
      powerpc/mpic: Don't reset affinity for secondary MPIC on boot · cc353c30
      Arnd Bergmann 提交于
      Kexec/kdump currently fails on the IBM QS2x blades when the kexec happens
      on a CPU other than the initial boot CPU.  It turns out that this is the
      result of mpic_init trying to set affinity of each interrupt vector to the
      current boot CPU.
      
      As far as I can tell,  the same problem is likely to exist on any
      secondary MPIC, because they have to deliver interrupts to the first
      output all the time. There are two potential solutions for this: either
      not set up affinity at all for secondary MPICs, or assume that a single
      CPU output is connected to the upstream interrupt controller and hardcode
      affinity to that per architecture.
      
      This patch implements the second approach, defaulting to the first output.
      Currently, all known secondary MPICs are routed to their upstream port
      using the first destination, so we hardcode that.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      cc353c30
    • A
      powerpc/cell/axon-msi: Retry on missing interrupt · d015fe99
      Arnd Bergmann 提交于
      The MSI capture logic for the axon bridge can sometimes
      lose interrupts in case of high DMA and interrupt load,
      when it signals an MSI interrupt to the MPIC interrupt
      controller while we are already handling another MSI.
      
      Each MSI vector gets written into a FIFO buffer in main
      memory using DMA, and that DMA access is normally flushed
      by the actual interrupt packet on the IOIF.  An MMIO
      register in the MSIC holds the position of the last
      entry in the FIFO buffer that was written.  However,
      reading that position does not flush the DMA, so that
      we can observe stale data in the buffer.
      
      In a stress test, we have observed the DMA to arrive
      up to 14 microseconds after reading the register.
      
      This patch works around this problem by retrying the
      access to the FIFO buffer.
      
      We can reliably detect the conditioning by writing
      an invalid MSI vector into the FIFO buffer after
      reading from it, assuming that all MSIs we get
      are valid.  After detecting an invalid MSI vector,
      we udelay(1) in the interrupt cascade for up to
      100 times before giving up.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      d015fe99
    • D
      powerpc: Fix boot freeze on machine with empty memory node · 4a618669
      Dave Hansen 提交于
      I got a bug report about a distro kernel not booting on a particular
      machine.  It would freeze during boot:
      
      > ...
      > Could not find start_pfn for node 1
      > [boot]0015 Setup Done
      > Built 2 zonelists in Node order, mobility grouping on.  Total pages: 123783
      > Policy zone: DMA
      > Kernel command line:
      > [boot]0020 XICS Init
      > [boot]0021 XICS Done
      > PID hash table entries: 4096 (order: 12, 32768 bytes)
      > clocksource: timebase mult[7d0000] shift[22] registered
      > Console: colour dummy device 80x25
      > console handover: boot [udbg0] -> real [hvc0]
      > Dentry cache hash table entries: 1048576 (order: 7, 8388608 bytes)
      > Inode-cache hash table entries: 524288 (order: 6, 4194304 bytes)
      > freeing bootmem node 0
      
      I've reproduced this on 2.6.27.7.  It is caused by commit
      8f64e1f2 ("powerpc: Reserve in bootmem
      lmb reserved regions that cross NUMA nodes").
      
      The problem is that Jon took a loop which was (in pseudocode):
      
      	for_each_node(nid)
      		NODE_DATA(nid) = careful_alloc(nid);
      		setup_bootmem(nid);
      		reserve_node_bootmem(nid);
      
      and broke it up into:
      
      	for_each_node(nid)
      		NODE_DATA(nid) = careful_alloc(nid);
      		setup_bootmem(nid);
      	for_each_node(nid)
      		reserve_node_bootmem(nid);
      
      The issue comes in when the 'careful_alloc()' is called on a node with
      no memory.  It falls back to using bootmem from a previously-initialized
      node.  But, bootmem has not yet been reserved when Jon's patch is
      applied.  It gives back bogus memory (0xc000000000000000) and pukes
      later in boot.
      
      The following patch collapses the loop back together.  It also breaks
      the mark_reserved_regions_for_nid() code out into a function and adds
      some comments.  I think a huge part of introducing this bug is because
      for loop was too long and hard to read.
      
      The actual bug fix here is the:
      
      +		if (end_pfn <= node->node_start_pfn ||
      +		    start_pfn >= node_end_pfn)
      +			continue;
      Signed-off-by: NDave Hansen <dave@linux.vnet.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      4a618669