Describe the PCI USB devices that are behind the PCI bridges, adding
necessary links to the USB PHY device.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Define the r8a7745 generic part of the USB PHY device node.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add device nodes for the r8a7745 internal PCI bridge devices.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The following 'capacity-dmips-mhz' dt property values are used:

Cortex-A15: 1024, Cortex-A7: 539

They have been derived form the cpu_efficiency values:

Cortex-A15: 3891, Cortex-A7: 2048

by scaling them so that the Cortex-A15s (big cores) use 1024.

The cpu_efficiency values were originally derived from the "Big.LITTLE
Processing with ARM Cortex™-A15 & Cortex-A7" white paper
(http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x
(3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the
Dhrystone benchmark.

The following platform is affected once cpu-invariant accounting
support is re-connected to the task scheduler:

r8a7790-lager
Signed-off-by: NDietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds a .dtsi that describes the camera daughter board
and a .dts to describe the HW made of iWave's RZ/G1M SoM, iWave's
RZ/G1M/G1N Qseven carrier board, and the camera daughter board.
The camera daughter board .dtsi adds support for ttySC[14].
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Since the same carrier board may host RZ/G1M and RZ/G1N based
Systems on Module, the DT architecture for iwg20d-q7 needs
better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier
  board definitions, and its content is basically the same
  as the previous version of r8a7743-iwg20d-q7.dts, only it
  has no reference to the SoM .dtsi, and that's why the
  filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together
  the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board
  .dtsi defined by this very patch, along with "model" and
  "compatible" properties.
The final DT architecture to describe the board is now:
r8a7743-iwg20d-q7.dts           # Carrier Board + SoM
├── r8a7743-iwg20m.dtsi         # SoM
│   └── r8a7743.dtsi            # SoC
└── iwg20d-q7-common.dtsi       # Carrier Board
and maximizes the reuse of the definitions for the carrier board
and for the SoM.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Use the preferred generic node name instead of the specific name.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Use the preferred generic node name instead of the specific name.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Use the preferred generic node name instead of the specific name.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Use the preferred generic node name instead of the specific name.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

MTU2 multi-function/multi-channel timer/counter is not enabled for
GR-Peach board. The timer is used as clock event source to schedule
wake-ups, and without this enabled all sleeps not performed through busy
waiting hang the board.
Signed-off-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Fix 'leds' node name indent as it was wrongly aligned.
Signed-off-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi.
Also, define aliases for spi[123].
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi.
Also, define aliases for spi[123].
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Enable the SDHI0 controller on iWave RZ/G1E carrier board.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add support for the SPI NOR device used to boot up the system
to the System on Module DT.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add the DT node for the QSPI interface to the SoC dtsi.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add support for the SPI NOR device used to boot up the system
to the System on Module DT.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add the DT node for the QSPI interface to the SoC dtsi.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Enable the SDHI1 controller on iWave RZ/G1E SoM.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add the SDHI controllers to the r8a7745 device tree.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add properties to describe the reset topology for on-SoC devices:
  - Add the "#reset-cells" property to the CPG/MSSR device node,
  - Add resets and reset-names properties to the various device nodes.

This allows to reset SoC devices using the Reset Controller API.

Note that resets usually match the corresponding module clocks.
Exceptions are:
  - The audio module has resets for the Serial Sound Interfaces only,
  - The display module has only a single reset for all DU channels, but
    adding reset properties for the display is postponed.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add properties to describe the reset topology for on-SoC devices:
  - Add the "#reset-cells" property to the CPG/MSSR device node,
  - Add resets and reset-names properties to the various device nodes.

This allows to reset SoC devices using the Reset Controller API.

Note that resets usually match the corresponding module clocks.
Exceptions are:
  - The audio module has resets for the Serial Sound Interfaces only,
  - The display module has only a single reset for all DU channels, but
    adding reset properties for the display is postponed.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add properties to describe the reset topology for on-SoC devices:
  - Add the "#reset-cells" property to the CPG/MSSR device node,
  - Add resets and reset-names properties to the various device nodes.

This allows to reset SoC devices using the Reset Controller API.

Note that resets usually match the corresponding module clocks.
Exceptions are:
  - The audio module has resets for the Serial Sound Interfaces only,
    but audio is not yet enabled in r8a7792.dtsi,
  - The display module has only a single reset for all DU channels, but
    adding reset properties for the display is postponed.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add properties to describe the reset topology for on-SoC devices:
  - Add the "#reset-cells" property to the CPG/MSSR device node,
  - Add resets and reset-names properties to the various device nodes.

This allows to reset SoC devices using the Reset Controller API.

Note that resets usually match the corresponding module clocks.
Exceptions are:
  - The audio module has resets for the Serial Sound Interfaces only,
  - The display module has only a single reset for all DU channels, but
    adding reset properties for the display is postponed.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add properties to describe the reset topology for on-SoC devices:
  - Add the "#reset-cells" property to the CPG/MSSR device node,
  - Add resets and reset-names properties to the various device nodes.

This allows to reset SoC devices using the Reset Controller API.

Note that resets usually match the corresponding module clocks.
Exceptions are:
  - The audio module has resets for the Serial Sound Interfaces only,
  - The display module has only a single reset for all DU channels, but
    adding reset properties for the display is postponed.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The WP pins are ACTIVE_HIGH, fix it in the DTS.

Fixes: 2b41091b ("ARM: dts: alt: add SDHI0 and 1 support")
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers
attached to them.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Describe the PCI USB devices that are behind the PCI bridges, adding
necessary links to the USB PHY device.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Define the r8a7743 generic part of the USB PHY device node.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add device nodes for the r8a7743 internal PCI bridge devices.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Define the iWave RainboW-G22D board dependent part of the Ethernet
AVB device node.

On some older versions of the platform (before R4.0) the phy address
may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which
will be the first mainstream release), hence using 3 in the dts.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Adding pinctrl support for scif4 interface.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Define the iWave RainboW-G20D-Qseven board dependent part of the
RTC device node.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add Ethernet AVB support for r8a7745 SoC.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add device nodes for user leds on gr-peach board.
Signed-off-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add pin configuration subnode for SCIF2 serial debug interface.
Signed-off-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>