1. 20 3月, 2013 1 次提交
    • J
      drm/i915: stop using GMBUS IRQs on Gen4 chips · c12aba5a
      Jiri Kosina 提交于
      Commit 28c70f16 ("drm/i915: use the gmbus irq for waits") switched to
      using GMBUS irqs instead of GPIO bit-banging for chipset generations 4
      and above.
      
      It turns out though that on many systems this leads to spurious interrupts
      being generated, long after the register write to disable the IRQs has been
      issued.
      
      Typically this results in the spurious interrupt source getting
      disabled:
      
      [    9.636345] irq 16: nobody cared (try booting with the "irqpoll" option)
      [    9.637915] Pid: 4157, comm: ifup Tainted: GF            3.9.0-rc2-00341-g08637024 #422
      [    9.639484] Call Trace:
      [    9.640731]  <IRQ>  [<ffffffff8109b40d>] __report_bad_irq+0x1d/0xc7
      [    9.640731]  [<ffffffff8109b7db>] note_interrupt+0x15b/0x1e8
      [    9.640731]  [<ffffffff810999f7>] handle_irq_event_percpu+0x1bf/0x214
      [    9.640731]  [<ffffffff81099a88>] handle_irq_event+0x3c/0x5c
      [    9.640731]  [<ffffffff8109c139>] handle_fasteoi_irq+0x7a/0xb0
      [    9.640731]  [<ffffffff8100400e>] handle_irq+0x1a/0x24
      [    9.640731]  [<ffffffff81003d17>] do_IRQ+0x48/0xaf
      [    9.640731]  [<ffffffff8142f1ea>] common_interrupt+0x6a/0x6a
      [    9.640731]  <EOI>  [<ffffffff8142f952>] ? system_call_fastpath+0x16/0x1b
      [    9.640731] handlers:
      [    9.640731] [<ffffffffa000d771>] usb_hcd_irq [usbcore]
      [    9.640731] [<ffffffffa0306189>] yenta_interrupt [yenta_socket]
      [    9.640731] Disabling IRQ #16
      
      The really curious thing is now that irq 16 is _not_ the interrupt for
      the i915 driver when using MSI, but it _is_ the interrupt when not
      using MSI. So by all indications it seems like gmbus is able to
      generate a legacy (shared) interrupt in MSI mode on some
      configurations. I've tried to reproduce this and the differentiating
      thing seems to be that on unaffected systems no other device uses irq
      16 (which seems to be the non-MSI intel gfx interrupt on all gm45).
      
      I have no idea how that even can happen.
      
      To avoid tempting this elephant into a rage, just disable gmbus
      interrupt support on gen 4.
      
      v2: Improve the commit message with exact details of what's going on.
      Also add a comment in the code to warn against this particular
      elephant in the room.
      
      v3: Move the comment explaing how gen4 blows up next to the definition
      of HAS_GMBUS_IRQ to keep the code-flow straight. Suggested by Chris
      Wilson.
      
      Signed-off-by: Jiri Kosina <jkosina@suse.cz> (v1)
      Acked-by: NChris Wilson <chris@chris-wilson.co.uk>
      References: https://lkml.org/lkml/2013/3/8/325Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      c12aba5a
  2. 18 3月, 2013 2 次提交
    • T
      drm/i915: Use the fixed pixel clock for eDP in intel_dp_set_m_n() · 9d1a455b
      Takashi Iwai 提交于
      The eDP output on HP Z1 is still broken when X is started even after
      fixing the infinite link-train loop.  The regression was introduced in
      3.6 kernel for cleaning up the mode clock handling code in intel_dp.c
      by the commit [71244653: drm/i915: adjusted_mode->clock in the dp
      mode_fix].
      
      In the past, the clock of the reference mode was modified in
      intel_dp_mode_fixup() in the case of eDP fixed clock, and this clock was
      used for calculating in intel_dp_set_m_n().  This override was removed,
      thus the wrong mode clock is used for the calculation, resulting in a
      psychedelic smoking output in the end.
      
      This patch corrects the clock to be used in the place.
      
      v1->v2: Use intel_edp_target_clock() for checking eDP fixed clock
      instead of open code as in ironlake_set_m_n().
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      9d1a455b
    • T
      Revert "drm/i915: try to train DP even harder" · 3b4f819d
      Takashi Iwai 提交于
      This reverts commit 0d710688.
      
      Not only that the commit introduces a bogus check (voltage_tries == 5
      will never meet at the inserted code path), it brings the i915 driver
      into an endless dp-train loop on HP Z1 desktop machine with IVY+eDP.
      
      At least reverting this commit recovers the framebuffer (but X is
      still broken by other reasons...)
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      3b4f819d
  3. 14 3月, 2013 2 次提交
  4. 08 3月, 2013 8 次提交
  5. 07 3月, 2013 1 次提交
  6. 06 3月, 2013 2 次提交
    • P
      drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bits · 60222c0c
      Patrik Jakobsson 提交于
      Disable bits for ADPA HSYNC and VSYNC where mixed up resulting in suspend
      becoming standby and vice versa. Fixed by swapping their bit position.
      Reported-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NPatrik Jakobsson <patrik.r.jakobsson@gmail.com>
      Reviewed-by: NEric Anholt <eric@anholt.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      60222c0c
    • P
      drm/i915: also disable south interrupts when handling them · 44498aea
      Paulo Zanoni 提交于
      From the docs:
      
        "IIR can queue up to two interrupt events. When the IIR is cleared,
        it will set itself again after one clock if a second event was
        stored."
      
        "Only the rising edge of the PCH Display interrupt will cause the
        North Display IIR (DEIIR) PCH Display Interrupt even bit to be set,
        so all PCH Display Interrupts, including back to back interrupts,
        must be cleared before a new PCH Display interrupt can cause DEIIR
        to be set".
      
      The current code works fine because we don't get many interrupts, but
      if we enable the PCH FIFO underrun interrupts we'll start getting so
      many interrupts that at some point new PCH interrupts won't cause
      DEIIR to be set.
      
      The initial implementation I tried was to turn the code that checks
      SDEIIR into a loop, but we can still get interrupts even after the
      loop is done (and before the irq handler finishes), so we have to
      either disable the interrupts or mask them. In the end I concluded
      that just disabling the PCH interrupts is enough, you don't even need
      the loop, so this is what this patch implements. I've tested it and it
      passes the 2 "PCH FIFO underrun interrupt storms" I can reproduce:
      the "ironlake_crtc_disable" case and the "wrong watermarks" case.
      
      In other words, here's how to reproduce the problem fixed by this
      patch:
        1 - Enable PCH FIFO underrun interrupts (SERR_INT on SNB+)
        2 - Boot the machine
        3 - While booting we'll get tons of PCH FIFO underrun interrupts
        4 - Plug a new monitor
        5 - Run xrandr, notice it won't detect the new monitor
        6 - Read SDEIIR and notice it's not 0 while DEIIR is 0
      
      Q: Can't we just clear DEIIR before SDEIIR?
      A: It doesn't work. SDEIIR has to be completely cleared (including the
      interrupts stored on its back queue) before it can flip DEIIR's bit to
      1 again, and even while you're clearing it you'll be getting more and
      more interrupts.
      
      Q: Why does it work by just disabling+enabling the south interrupts?
      A: Because when we re-enable them, if there's something on the SDEIIR
      register (maybe an interrupt stored on the queue), the re-enabling
      will make DEIIR's bit flip to 1, and since we'll already have
      interrupts enabled we'll get another interrupt, then run our irq
      handler again to process the "back" interrupts.
      
      v2: Even bigger commit message, added code comments.
      
      Note that this fixes missed dp aux irqs which have been reported for
      3.9-rc1. This regression has been introduced by switching to
      irq-driven dp aux transactions with
      
      commit 9ee32fea
      Author: Daniel Vetter <daniel.vetter@ffwll.ch>
      Date:   Sat Dec 1 13:53:48 2012 +0100
      
          drm/i915: irq-drive the dp aux communication
      
      References: http://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg18588.html
      References: https://lkml.org/lkml/2013/2/26/769Tested-by: NImre Deak <imre.deak@intel.com>
      Reported-by: NSedat Dilek <sedat.dilek@gmail.com>
      Reported-by: NLinus Torvalds <torvalds@linux-foundation.org>
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      [danvet: Pimp commit message with references for the dp aux irq
      timeout regression this fixes.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      44498aea
  7. 05 3月, 2013 3 次提交
  8. 04 3月, 2013 10 次提交
  9. 28 2月, 2013 8 次提交
  10. 26 2月, 2013 1 次提交
  11. 23 2月, 2013 1 次提交
  12. 22 2月, 2013 1 次提交
    • D
      drm/i915: Revert hdmi HDP pin checks · 202adf4b
      Daniel Vetter 提交于
      This reverts
      
      commit 8ec22b21
      Author: Chris Wilson <chris@chris-wilson.co.uk>
      Date:   Fri May 11 18:01:34 2012 +0100
      
          drm/i915/hdmi: Query the live connector status bit for G4x
      
      and
      
      commit b0ea7d37
      Author: Damien Lespiau <damien.lespiau@intel.com>
      Date:   Thu Dec 13 16:09:00 2012 +0000
      
          drm/i915/hdmi: Read the HPD status before trying to read the EDID
      
      They reliably cause HDMI to not be detected on some systems (like my
      ivb or the bug reporters gm45). To fix up the very slow unplug issues
      we might want to fire up a 2nd detect cycle a few hundred ms after
      each hotplug. But for now at least make displays work again.
      
      I somewhat suspect that this is confined to HDMI connectors, since all
      the machines I have with DP+ outputs work correctly.
      
      Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=52361
      Cc: Damien Lespiau <damien.lespiau@intel.com>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Acked-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: stable@vger.kernel.org.kernel.org # for 8ec22b21Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      202adf4b