1. 11 2月, 2010 1 次提交
    • Z
      drm/i915: Rework DPLL calculation parameters for Ironlake · b91ad0ec
      Zhenyu Wang 提交于
      Got Ironlake DPLL parameter table, which reflects the hardware
      optimized values. So this one trys to list DPLL parameters for
      different output types, should potential fix clock issue seen
      on new Arrandale CPUs.
      
      This fixes DPLL setting failure on one 1920x1080 dual channel
      LVDS for Ironlake. Test has also been made on LVDS panels with
      smaller size and CRT/HDMI/DP ports for different monitors on
      their all supported modes.
      
      Update:
      - Change name of double LVDS to dual LVDS.
      - Fix SSC 120M reference clock to use the right range.
      
      Cc: CSJ <changsijay@gmail.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: NEric Anholt <eric@anholt.net>
      b91ad0ec
  2. 10 2月, 2010 14 次提交
  3. 09 2月, 2010 25 次提交