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  1. 14 12月, 2017 3 次提交
    • G
      spi: sh-msiof: Implement cs-gpios configuration · b8761434
      由 Geert Uytterhoeven 提交于 
      The current support for GPIO chip selects assumes the GPIOs have been
configured by platform code or the boot loader.  This includes pinmux
setup and GPIO direction.  Hence it does not work as expected when just
described in DT using the "cs-gpios" property.

Fix this by:
  1. using devm_gpiod_get_index() to request the GPIO, and thus
     configure pinmux, if needed,
  2. configuring the GPIO direction is the spi_master.setup() callback.

Use gpio_is_valid() instead of a check on positive numbers.

Note that when using GPIO chip selects, at least one native chip select
must be left unused, as that native chip select will be driven anyway,
and (global) native chip select polarity must be taken into account.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NMark Brown <broonie@kernel.org>
      b8761434
    • G
      spi: sh-msiof: Extend support to 3 native chip selects · 9cce882b
      由 Geert Uytterhoeven 提交于 
      Currently only the MSIOF_SYNC signal can be used as a native chip
select.  Extend support to up to 3 native chipselects using the
MSIOF_SS1 and MSIOF_SS2 signals.

Inspired by a patch in the BSP by Hiromitsu Yamasaki.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NMark Brown <broonie@kernel.org>
      9cce882b
    • G
      spi: sh-msiof: Avoid writing to registers from spi_master.setup() · 7ff0b53c
      由 Geert Uytterhoeven 提交于 
      The spi_master.setup() callback must not change configuration registers,
as that could corrupt I/O that is in progress for other SPI slaves.

The only exception is the configuration of the native chip select
polarity in SPI master mode, as a wrong chip select polarity will cause
havoc during all future transfers to any other SPI slave.

Hence stop writing to registers in sh_msiof_spi_setup(), unless it is
the first call for a controller using a native chip select, or unless
native chip select polarity has changed (note that you'll loose anyway
if I/O is in progress).  Even then, only do what is strictly necessary,
instead of calling sh_msiof_spi_set_pin_regs().
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NMark Brown <broonie@kernel.org>
      7ff0b53c
  3. 01 12月, 2017 1 次提交
  5. 04 11月, 2017 1 次提交
  7. 02 11月, 2017 1 次提交
  9. 04 10月, 2017 1 次提交
  11. 26 9月, 2017 1 次提交
  13. 17 7月, 2017 1 次提交
  15. 26 5月, 2017 1 次提交
  17. 05 1月, 2017 1 次提交
  19. 20 12月, 2016 1 次提交
  21. 15 12月, 2016 1 次提交
    • S
      spi: sh-msiof: Add R-Car Gen 2 and 3 fallback bindings · 4286db84
      由 Simon Horman 提交于 
      In the case of Renesas R-Car hardware we know that there are generations of
SoCs, e.g. Gen 2 and Gen 3. But beyond that it's not clear what the
relationship between IP blocks might be. For example, I believe that
r8a7790 is older than r8a7791 but that doesn't imply that the latter is a
descendant of the former or vice versa.

We can, however, by examining the documentation and behaviour of the
hardware at run-time observe that the current driver implementation appears
to be compatible with the IP blocks on SoCs within a given generation.

For the above reasons and convenience when enabling new SoCs a
per-generation fallback compatibility string scheme is being adopted for
drivers for Renesas SoCs.

Also:
* Deprecate renesas,sh-msiof. It seems poorly named as it is only
  compatible with SH-Mobile. It also appears unused in mainline.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NMark Brown <broonie@kernel.org>
      4286db84
  23. 22 11月, 2016 1 次提交
  25. 05 8月, 2016 1 次提交
  27. 22 6月, 2016 1 次提交
  29. 31 8月, 2015 1 次提交
  31. 07 7月, 2015 1 次提交
  33. 02 5月, 2015 1 次提交
  35. 23 2月, 2015 1 次提交
  37. 05 2月, 2015 1 次提交
  39. 03 2月, 2015 1 次提交
  41. 08 1月, 2015 1 次提交
  43. 06 1月, 2015 1 次提交
  45. 24 12月, 2014 1 次提交
  47. 16 12月, 2014 1 次提交
  49. 20 10月, 2014 1 次提交
  51. 31 8月, 2014 1 次提交
  53. 29 8月, 2014 1 次提交
  55. 17 8月, 2014 5 次提交
  57. 17 7月, 2014 2 次提交
  59. 01 7月, 2014 1 次提交
    • G
      spi: sh-msiof: Add DMA support · b0d0ce8b
      由 Geert Uytterhoeven 提交于 
      Add DMA support to the MSIOF driver using platform data.

As MSIOF DMA is limited to 32-bit words (requiring byte/wordswapping for
smaller wordsizes), and the group length is limited to 256 words, DMA is
performed on two fixed pages, allocated and mapped at driver initialization
time.

Performance figures (in Mbps) on r8a7791/koelsch at different SPI clock
frequencies for 1024-byte and 4096-byte transfers:

                   1024 bytes           4096 bytes
  -  3.25 MHz: PIO  2.1, DMA  2.6 | PIO  2.8, DMA  3.1
  -  6.5  MHz: PIO  3.2, DMA  4.4 | PIO  5.0, DMA  5.9
  - 13    MHz: PIO  4.2, DMA  6.6 | PIO  8.2, DMA 10.7
  - 26    MHz: PIO  5.9, DMA 10.4 | PIO 12.4, DMA 18.4

Note that DMA is only faster than PIO for transfers that exceed the FIFO
size (typically 64 words / 256 bytes).

Also note that large transfers (larger than the group length for DMA, or
larger than the FIFO size for PIO), should use cs-gpio (with the
appropriate pinmux setup), as the hardware chipselect will be deasserted in
between chunks.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NMark Brown <broonie@linaro.org>
      b0d0ce8b
  61. 21 6月, 2014 3 次提交