1. 08 9月, 2012 1 次提交
  2. 25 8月, 2012 2 次提交
  3. 23 8月, 2012 8 次提交
    • S
      ARM: perf: move irq registration into pmu implementation · 051f1b13
      Sudeep KarkadaNagesha 提交于
      This patch moves the CPU-specific IRQ registration and parsing code into
      the CPU PMU backend. This is required because a PMU may have more than
      one interrupt, which in turn can be either PPI (per-cpu) or SPI
      (requiring strict affinity setting at the interrupt distributor).
      Signed-off-by: NSudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
      [will: cosmetic edits and reworked interrupt dispatching]
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      051f1b13
    • W
      ARM: perf: move CPU-specific PMU handling code into separate file · 5505b206
      Will Deacon 提交于
      This patch moves the CPU-specific PMU handling code out of perf_event.c
      and into perf_event_cpu.c.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      5505b206
    • W
      ARM: perf: prepare for moving CPU PMU code into separate file · 6dbc0029
      Will Deacon 提交于
      The CPU PMU code is tightly coupled with generic ARM PMU handling code.
      This makes it cumbersome when trying to add support for other ARM PMUs
      (e.g. interconnect, L2 cache controller, bus) as the generic parts of
      the code are not readily reusable.
      
      This patch cleans up perf_event.c so that reusable code is exposed via
      header files to other potential PMU drivers. The CPU code is
      consistently named to identify it as such and also to prepare for moving
      it into a separate file.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      6dbc0029
    • W
      ARM: perf: probe devicetree in preference to current CPU · 04236f9f
      Will Deacon 提交于
      The CPU PMU is probed using the current cpuid information as part of the
      early_initcall initialising the architecture perf backend. For
      architectures without NMI (such as ARM), this does not need to be
      performed early and can be deferred to the driver probe callback. This
      also allows us to probe the devicetree in preference to parsing the
      current cpuid, which may be invalid on a big.LITTLE multi-cluster
      system.
      
      This patch defers the PMU probing and uses the devicetree information
      when available.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      04236f9f
    • W
      ARM: perf: remove mysterious compiler barrier · 9f44f9a2
      Will Deacon 提交于
      There's a rather strange compiler barrier in the PMU disabling code
      which was presumably placed there by aliens. There's no valid reason for
      the barrier and one can only suspect that it's up to no good.
      
      This patch removes it before it has a chance to spread.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      9f44f9a2
    • W
      ARM: pmu: remove unused reservation mechanism · f0d1bc47
      Will Deacon 提交于
      The PMU reservation mechanism was originally intended to allow OProfile
      and perf-events to co-ordinate over access to the CPU PMU. Since then,
      OProfile for ARM has moved to using perf as its backend, so the
      reservation code is no longer used.
      
      This patch removes the reservation code for the CPU PMU on ARM.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      f0d1bc47
    • W
      ARM: perf: add devicetree bindings for 11MPcore, A5, A7 and A15 PMUs · 50243efd
      Will Deacon 提交于
      This patch adds separate devicetree bindings for 11MPcore and
      Cortex-{A5,A7,A15} PMUs in preparation for improved devicetree parsing
      in the ARM perf-event CPU PMU driver.
      
      Cc: Grant Likely <grant.likely@secretlab.ca>
      Acked-by: NRob Herring <rob.herring@calxeda.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      50243efd
    • J
      ARM: PMU: Add runtime PM Support · 7be2958e
      Jon Hunter 提交于
      Add runtime PM support to the ARM PMU driver so that devices such as OMAP
      supporting dynamic PM can use the platform->runtime_* hooks to initialise
      hardware at runtime. Without having these runtime PM hooks in place any
      configuration of the PMU hardware would be lost when low power states are
      entered and hence would prevent PMU from working.
      
      This change also replaces the PMU platform functions enable_irq and disable_irq
      added by Ming Lei with runtime_resume and runtime_suspend funtions. Ming had
      added the enable_irq and disable_irq functions as a method to configure the
      cross trigger interface on OMAP4 for routing the PMU interrupts. By adding
      runtime PM support, we can move the code called by enable_irq and disable_irq
      into the runtime PM callbacks runtime_resume and runtime_suspend.
      
      Cc: Ming Lei <ming.lei@canonical.com>
      Cc: Benoit Cousson <b-cousson@ti.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      7be2958e
  4. 11 8月, 2012 2 次提交
  5. 31 7月, 2012 4 次提交
    • R
      ARM: Fix undefined instruction exception handling · 15ac49b6
      Russell King 提交于
      While trying to get a v3.5 kernel booted on the cubox, I noticed that
      VFP does not work correctly with VFP bounce handling.  This is because
      of the confusion over 16-bit vs 32-bit instructions, and where PC is
      supposed to point to.
      
      The rule is that FP handlers are entered with regs->ARM_pc pointing at
      the _next_ instruction to be executed.  However, if the exception is
      not handled, regs->ARM_pc points at the faulting instruction.
      
      This is easy for ARM mode, because we know that the next instruction and
      previous instructions are separated by four bytes.  This is not true of
      Thumb2 though.
      
      Since all FP instructions are 32-bit in Thumb2, it makes things easy.
      We just need to select the appropriate adjustment.  Do this by moving
      the adjustment out of do_undefinstr() into the assembly code, as only
      the assembly code knows whether it's dealing with a 32-bit or 16-bit
      instruction.
      
      Cc: <stable@vger.kernel.org>
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      15ac49b6
    • J
      ARM: 7480/1: only call smp_send_stop() on SMP · c5dff4ff
      Javier Martinez Canillas 提交于
      On reboot or poweroff (machine_shutdown()) a call to smp_send_stop() is
      made (to stop the others CPU's) when CONFIG_SMP=y.
      
      arch/arm/kernel/process.c:
      
      void machine_shutdown(void)
      {
       #ifdef CONFIG_SMP
             smp_send_stop();
       #endif
      }
      
      smp_send_stop() calls the function pointer smp_cross_call(), which is set
      on the smp_init_cpus() function for OMAP processors.
      
      arch/arm/mach-omap2/omap-smp.c:
      
      void __init smp_init_cpus(void)
      {
      ...
      	set_smp_cross_call(gic_raise_softirq);
      ...
      }
      
      But the ARM setup_arch() function only calls smp_init_cpus()
      if CONFIG_SMP=y && is_smp().
      
      arm/kernel/setup.c:
      
      void __init setup_arch(char **cmdline_p)
      {
      ...
       #ifdef CONFIG_SMP
      	if (is_smp())
      		smp_init_cpus();
       #endif
      ...
      }
      
      Newer OMAP CPU's are SMP machines so omap2plus_defconfig sets
      CONFIG_SMP=y. Unfortunately on an OMAP UP machine is_smp()
      returns false and smp_init_cpus() is never called and the
      smp_cross_call() function remains NULL.
      
      If the machine is rebooted or powered off, smp_send_stop() will
      be called (since CONFIG_SMP=y) leading to the following error:
      
      [   42.815551] Restarting system.
      [   42.819030] Unable to handle kernel NULL pointer dereference at virtual address 00000000
      [   42.827667] pgd = d7a74000
      [   42.830566] [00000000] *pgd=96ce7831, *pte=00000000, *ppte=00000000
      [   42.837249] Internal error: Oops: 80000007 [#1] SMP ARM
      [   42.842773] Modules linked in:
      [   42.846008] CPU: 0    Not tainted  (3.5.0-rc3-next-20120622-00002-g62e87ba-dirty #44)
      [   42.854278] PC is at 0x0
      [   42.856994] LR is at smp_send_stop+0x4c/0xe4
      [   42.861511] pc : [<00000000>]    lr : [<c00183a4>]    psr: 60000013
      [   42.861511] sp : d6c85e70  ip : 00000000  fp : 00000000
      [   42.873626] r10: 00000000  r9 : d6c84000  r8 : 00000002
      [   42.879150] r7 : c07235a0  r6 : c06dd2d0  r5 : 000f4241  r4 : d6c85e74
      [   42.886047] r3 : 00000000  r2 : 00000000  r1 : 00000006  r0 : d6c85e74
      [   42.892944] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
      [   42.900482] Control: 10c5387d  Table: 97a74019  DAC: 00000015
      [   42.906555] Process reboot (pid: 1166, stack limit = 0xd6c842f8)
      [   42.912902] Stack: (0xd6c85e70 to 0xd6c86000)
      [   42.917510] 5e60:                                     c07235a0 00000000 00000000 d6c84000
      [   42.926177] 5e80: 01234567 c00143d0 4321fedc c00511bc d6c85ebc 00000168 00000460 00000000
      [   42.934814] 5ea0: c1017950 a0000013 c1017900 d8014390 d7ec3858 c0498e48 c1017950 00000000
      [   42.943481] 5ec0: d6ddde10 d6c85f78 00000003 00000000 d6ddde10 d6c84000 00000000 00000000
      [   42.952117] 5ee0: 00000002 00000000 00000000 c0088c88 00000002 00000000 00000000 c00f4b90
      [   42.960784] 5f00: 00000000 d6c85ebc d8014390 d7e311c8 60000013 00000103 00000002 d6c84000
      [   42.969421] 5f20: c00f3274 d6e00a00 00000001 60000013 d6c84000 00000000 00000000 c00895d4
      [   42.978057] 5f40: 00000002 d8007c80 d781f000 c00f6150 d8010cc0 c00f3274 d781f000 d6c84000
      [   42.986694] 5f60: c0013020 d6e00a00 00000001 20000010 0001257c ef000000 00000000 c00895d4
      [   42.995361] 5f80: 00000002 00000001 00000003 00000000 00000001 00000003 00000000 00000058
      [   43.003997] 5fa0: c00130c8 c0012f00 00000001 00000003 fee1dead 28121969 01234567 00000002
      [   43.012634] 5fc0: 00000001 00000003 00000000 00000058 00012584 0001257c 00000001 00000000
      [   43.021270] 5fe0: 000124bc bec5cc6c 00008f9c 4a2f7c40 20000010 fee1dead 00000000 00000000
      [   43.029968] [<c00183a4>] (smp_send_stop+0x4c/0xe4) from [<c00143d0>] (machine_restart+0xc/0x4c)
      [   43.039154] [<c00143d0>] (machine_restart+0xc/0x4c) from [<c00511bc>] (sys_reboot+0x144/0x1f0)
      [   43.048278] [<c00511bc>] (sys_reboot+0x144/0x1f0) from [<c0012f00>] (ret_fast_syscall+0x0/0x3c)
      [   43.057464] Code: bad PC value
      [   43.060760] ---[ end trace c3988d1dd0b8f0fb ]---
      
      Add a check so smp_cross_call() is only called when there is more than one CPU on-line.
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: Javier Martinez Canillas <javier at dowhile0.org>
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      c5dff4ff
    • C
      ARM: 7468/1: ftrace: Trace function entry before updating index · 4c36595e
      Colin Cross 提交于
      Commit 722b3c74 modified x86 ftrace to
      avoid tracing all functions called from irqs when function graph was
      used with a filter.  Port the same fix to ARM.
      Acked-by: NSteven Rostedt <rostedt@goodmis.org>
      Signed-off-by: NColin Cross <ccross@android.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      4c36595e
    • S
      ARM: 7466/1: disable interrupt before spinning endlessly · 98bd8b96
      Shawn Guo 提交于
      The CPU will endlessly spin at the end of machine_halt and
      machine_restart calls.  However, this will lead to a soft lockup
      warning after about 20 seconds, if CONFIG_LOCKUP_DETECTOR is enabled,
      as system timer is still alive.
      
      Disable interrupt before going to spin endlessly, so that the lockup
      warning will never be seen.
      
      Cc: <stable@vger.kernel.org>
      Reported-by: NMarek Vasut <marex@denx.de>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      98bd8b96
  6. 30 7月, 2012 1 次提交
  7. 28 7月, 2012 6 次提交
  8. 26 7月, 2012 1 次提交
  9. 25 7月, 2012 1 次提交
    • R
      ARM: Add fixed PCI i/o mapping · c2794437
      Rob Herring 提交于
      This adds a fixed virtual mapping for PCI i/o addresses. The mapping is
      located at the last 2MB of vmalloc region (0xfee00000-0xff000000). 2MB
      is used to align with PMD size, but IO_SPACE_LIMIT is 1MB. The space
      is reserved after .map_io and can be mapped at any time later with
      pci_ioremap_io. Platforms which need early i/o mapping (e.g. for vga
      console) can call pci_map_io_early in their .map_io function.
      
      This has changed completely from the 1st implementation which only
      supported creating the static mapping at .map_io.
      Signed-off-by: NRob Herring <rob.herring@calxeda.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Acked-by: NNicolas Pitre <nico@linaro.org>
      c2794437
  10. 13 7月, 2012 3 次提交
  11. 10 7月, 2012 11 次提交