1. 11 10月, 2007 6 次提交
  2. 08 10月, 2007 1 次提交
    • R
      Longhaul: add auto enabled "revid_errata" option · 52a2638b
      Rafal Bilski 提交于
      VIA C3 Ezra-T has RevisionID equal to 1, but it needs RevisionKey to be 0
      or CPU will ignore new frequency and will continue to work at old
      frequency.  New "revid_errata" option will force RevisionKey to be set to
      0, whatever RevisionID is.
      
      Additionaly "Longhaul" will not silently ignore unsuccessful transition.
      It will try to check if "revid_errata" or "disable_acpi_c3" options need to
      be enabled for this processor/system.
      
      Same for Longhaul ver.  2 support.  It will be disabled if none of above
      options will work.
      
       Best case scenario (with patch apllied and v2 enabled):
       longhaul: VIA C3 'Ezra' [C5C] CPU detected.  Longhaul v2 supported.
       longhaul: Using northbridge support.
       longhaul: VRM 8.5
       longhaul: Max VID=1.350  Min VID=1.050, 13 possible voltage scales
       longhaul: f: 300000 kHz, index: 0, vid: 1050 mV
       [...]
       longhaul: Voltage scaling enabled.
       Worst case scenario:
       longhaul: VIA C3 'Ezra-T' [C5M] CPU detected.  Powersaver supported.
       longhaul: Using northbridge support.
       longhaul: Using ACPI support.
       longhaul: VRM 8.5
       longhaul: Claims to support voltage scaling but min & max are both 1.250. Voltage scaling disabled
       longhaul: Failed to set requested frequency!
       longhaul: Enabling "Ignore Revision ID" option.
       longhaul: Failed to set requested frequency!
       longhaul: Disabling ACPI C3 support.
       longhaul: Disabling "Ignore Revision ID" option.
       longhaul: Failed to set requested frequency!
       longhaul: Enabling "Ignore Revision ID" option.
      
      [akpm@linux-foundation.org: coding-style cleanups]
      Signed-off-by: NRafal Bilski <rafalbilski@interia.pl>
      Signed-off-by: NDave Jones <davej@redhat.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      52a2638b
  3. 29 9月, 2007 1 次提交
    • H
      [x86 setup] Correct the SMAP check for INT 0x15, AX=0xe820 · 4ee5b10a
      H. Peter Anvin 提交于
      The e820 probe code was checking %edx, not %eax, for the SMAP
      signature on return.  This worked on *almost* all systems, since %edx
      still contained SMAP from the call on entry, but on a handful of
      systems it failed -- plus, we would have missed real mismatches.
      
      The error output is "=d" to make sure gcc knows %edx is clobbered
      here.
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      4ee5b10a
  4. 27 9月, 2007 2 次提交
  5. 21 9月, 2007 3 次提交
  6. 20 9月, 2007 1 次提交
  7. 13 9月, 2007 2 次提交
  8. 12 9月, 2007 1 次提交
    • A
      revert "highmem: catch illegal nesting" · 4150d3f5
      Andrew Morton 提交于
      Revert
      
      	commit 656dad31
      	Author: Ingo Molnar <mingo@elte.hu>
      	Date:   Sat Feb 10 01:46:36 2007 -0800
      
      	[PATCH] highmem: catch illegal nesting
      
      	Catch illegally nested kmap_atomic()s even if the page that is mapped by
      	the 'inner' instance is from lowmem.
      
      	This avoids spuriously zapped kmap-atomic ptes and turns hard to find
      	crashes into clear asserts at the bug site.
      
      Problem is, a get_zeroed_page(GFP_KERNEL) from interrupt context will trigger
      this check if non-irq code on this CPU holds a KM_USER0 mapping.  But that
      get_zeroed_page() will never be altering the kmap slot anyway due to the
      GFP_KERNEL.
      
      Cc: Christoph Lameter <clameter@sgi.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      4150d3f5
  9. 11 9月, 2007 6 次提交
  10. 05 9月, 2007 1 次提交
    • C
      [x86 setup] Work around bug in Xen HVM · ce29a1f8
      Christian Ehrhardt 提交于
      Apparently XEN does not keep the contents of the 48-bit gdt_48 data
      structure that is passed to lgdt in the XEN machine state. Instead it
      appears to save the _address_ of the 48-bit descriptor
      somewhere. Unfortunately this data happens to reside on the stack and
      is probably no longer availiable at the time of the actual protected
      mode jump.
      
      This is Xen bug but given that there is a one-line patch to work
      around this problem, the linux kernel should probably do this.  My fix
      is to make the gdt_48 description in setup_gdt static (in setup_idt
      this is already the case). This allows the kernel to boot under
      Xen HVM again.
      Signed-off-by: NChristian Ehrhardt <lk@c--e.de>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      ce29a1f8
  11. 01 9月, 2007 2 次提交
    • L
      x86: be even more careful about checking the stack frame on dumping · 36ad4885
      Linus Torvalds 提交于
      lguest didn't initialize the kernel stack the way a real i386 kernel
      does, and ended up triggering a corner-case in the stack frame checking
      that doesn't happen on naive i386, and that the stack dumping didn't
      handle quite right.
      
      This makes the frame handling more correct, and tries to clarify the
      code at the same time so that it's a bit more obvious what is going on.
      
      Thanks to Rusty Russell for debugging the lguest failure-
      
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      36ad4885
    • H
      [x86 setup] Don't rely on the VESA BIOS being register-clean · 4221d014
      H. Peter Anvin 提交于
      The VESA BIOS is specified to be register-clean.  However, we have now
      found at least one system which violates that.  Thus, be as paranoid
      about VESA calls as about everything else.
      
      Huge thanks to Will Simoneau for reporting, diagnosing, and testing
      this out on Dell Inspiron 5150.
      
      Cc: Will Simoneau <simoneau@ele.uri.edu>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      4221d014
  12. 31 8月, 2007 1 次提交
    • D
      hugepage: fix broken check for offset alignment in hugepage mappings · dec4ad86
      David Gibson 提交于
      For hugepage mappings, the file offset, like the address and size, needs to
      be aligned to the size of a hugepage.
      
      In commit 68589bc3, the check for this was
      moved into prepare_hugepage_range() along with the address and size checks.
       But since BenH's rework of the get_unmapped_area() paths leading up to
      commit 4b1d8929, prepare_hugepage_range()
      is only called for MAP_FIXED mappings, not for other mappings.  This means
      we're no longer ever checking for an aligned offset - I've confirmed that
      mmap() will (apparently) succeed with a misaligned offset on both powerpc
      and i386 at least.
      
      This patch restores the check, removing it from prepare_hugepage_range()
      and putting it back into hugetlbfs_file_mmap().  I'm putting it there,
      rather than in the get_unmapped_area() path so it only needs to go in one
      place, than separately in the half-dozen or so arch-specific
      implementations of hugetlb_get_unmapped_area().
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Cc: Adam Litke <agl@us.ibm.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      dec4ad86
  13. 24 8月, 2007 2 次提交
    • H
      [x86 setup] Make sure AH=00h when setting a video mode · 71351b98
      H. Peter Anvin 提交于
      Passing a u8 into a register doesn't mean gcc will zero-extend it.
      Also, don't depend on thhe register not to change.
      
      Per bug report from Saul Tamari.
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      71351b98
    • H
      [x86 setup] Volatilize asm() statements · b015124e
      H. Peter Anvin 提交于
      asm() statements need to be volatile when:
      
      a. They have side effects (other than value returned).
      b. When the value returned can vary over time.
      c. When they have ordering constraints that cannot be expressed to gcc.
      
      In particular, the keyboard and timer reads were violating constraint (b),
      which resulted in the keyboard/timeout poll getting
      loop-invariant-removed when compiling with gcc 4.2.0.
      
      Thanks to an anonymous bug reporter for pointing this out.
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      b015124e
  14. 23 8月, 2007 3 次提交
  15. 22 8月, 2007 1 次提交
  16. 21 8月, 2007 1 次提交
    • L
      ACPI: boot correctly with "nosmp" or "maxcpus=0" · 61ec7567
      Len Brown 提交于
      In MPS mode, "nosmp" and "maxcpus=0" boot a UP kernel with IOAPIC disabled.
      However, in ACPI mode, these parameters didn't completely disable
      the IO APIC initialization code and boot failed.
      
      init/main.c:
      	Disable the IO_APIC if "nosmp" or "maxcpus=0"
      	undefine disable_ioapic_setup() when it doesn't apply.
      
      i386:
      	delete ioapic_setup(), it was a duplicate of parse_noapic()
      	delete undefinition of disable_ioapic_setup()
      
      x86_64:
      	rename disable_ioapic_setup() to parse_noapic() to match i386
      	define disable_ioapic_setup() in header to match i386
      
      http://bugzilla.kernel.org/show_bug.cgi?id=1641Acked-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      61ec7567
  17. 19 8月, 2007 4 次提交
  18. 15 8月, 2007 2 次提交
    • H
      [x86 setup] edd.c: make sure MBR signatures actually get reported · 9a5f35d4
      H. Peter Anvin 提交于
      When filling in the MBR signature array, the setup code failed to advance
      boot_params.edd_mbr_sig_buf_entries, which resulted in the valid data
      being ignored.
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      9a5f35d4
    • H
      [x86 setup] Don't use EDD to get the MBR signature · c1a6e2b0
      H. Peter Anvin 提交于
      At least one machine has been identified in the field which advertises
      EDD for all drives but locks up if one attempts an extended read from
      a non-primary drive.
      
      The MBR is always at CHS 0-0-1, so there is no reason to use an
      extended read, other than the possibility that the BIOS cannot handle
      it.
      
      Although this might break as many machines as it fixes (a small number
      either way), the current state is a regression but the reverse is not.
      Therefore revert to the previous state of not using extended read.
      
      Quite probably the Right Thing to do is to read using plain (CHS) read
      and extended read on failure, but that change would definitely have to
      go through -mm first.
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      c1a6e2b0