Merge tag 'tegra-for-4.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

soc: tegra: Core SoC changes for v4.10-rc1

This contains mostly cleanup and new feature work on the power
management controller as well as the addition of a Kconfig symbol for
the new Tegra186 (Parker) SoC generation.

* tag 'tegra-for-4.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Use consistent naming for PM domains
  soc/tegra: pmc: Remove genpd when adding provider fails
  soc/tegra: pmc: Check return code for pm_genpd_init()
  soc/tegra: pmc: Clean-up I/O rail error messages
  soc/tegra: pmc: Simplify IO rail bit handling
  soc/tegra: pmc: Guard against uninitialised PMC clock
  soc/tegra: pmc: Add I/O pad voltage support
  soc/tegra: pmc: Use consistent ordering of bit definitions
  soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()
  soc/tegra: pmc: Use BIT macro for register field definition
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'tegra-for-4.10-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

bus: Add Tegra GMI support

This provides a driver to enable the use of the Generic Memory Interface
found on Tegra SoCs that can host various types of high-speed devices.

* tag 'tegra-for-4.10-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  bus: Add support for Tegra Generic Memory Interface
  dt/bindings: Add bindings for Tegra GMI controller
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'tegra-for-4.10-reset' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

reset: Add Tegra BPMP reset driver

This contains a patch which implements a reset driver using the services
provided by the BPMP firmware (via the MRQ_RESET request).

* tag 'tegra-for-4.10-reset' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  reset: Add Tegra BPMP reset driver
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'tegra-for-4.10-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

firmware: Add Tegra IVC and BPMP support

IVC is an inter-processor communication protocol that uses shared memory
to exchange data between processors. The BPMP driver makes use of this
to communicate with the Boot and Power Management Processor (BPMP) and
uses an additional hardware synchronization primitive from the HSP block
to signal availability of new data (doorbell).

Firmware running on the BPMP implements a number of services such as the
control of clocks and resets within the system, or the ability to ungate
or gate power partitions.

* tag 'tegra-for-4.10-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: firmware: Allow child nodes inside the Tegra BPMP
  dt-bindings: Add power domains to Tegra BPMP firmware
  firmware: tegra: Add BPMP support
  firmware: tegra: Add IVC library
  dt-bindings: firmware: Add bindings for Tegra BPMP
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'tegra-for-4.10-mailbox' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

mailbox: Add Tegra HSP driver

This contains the device tree bindings and a driver for the Tegra HSP, a
hardware block that provides hardware synchronization primitives and is
the foundation for inter-processor communication between CPU and BPMP.

* tag 'tegra-for-4.10-mailbox' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells()
  mailbox: Add Tegra HSP driver
  dt-bindings: mailbox: Add Tegra HSP binding
  soc/tegra: Add Tegra186 support
Signed-off-by: NOlof Johansson <olof@lixom.net>

Reset controller changes for v4.10

- remove obsolete STiH41[56] platform support
- add Oxford Semiconductor OX820 support
- add reset index include files for OX810SE and OX820
- make drivers with boolean Kconfig options explicitly
  non-modular
- allow shared pulsed resets via reset_control_reset, which
  in this case means that the reset must have been triggered
  once, but possibly earlier, after the function returns, and
  is never triggered again for the lifetime of the reset
  control

* tag 'reset-for-4.10' of git://git.pengutronix.de/git/pza/linux:
  reset: allow using reset_control_reset with shared reset
  reset: lpc18xx: make it explicitly non-modular
  reset: zynq: make it explicitly non-modular
  reset: sunxi: make it explicitly non-modular
  reset: socfpga: make it explicitly non-modular
  reset: berlin: make it explicitly non-modular
  dt-bindings: reset: oxnas: Update for OX820
  dt-bindings: reset: oxnas: Add include file with reset indexes
  reset: oxnas: Add OX820 support
  reset: sti: softreset: Remove obsolete platforms from dt binding doc.
  reset: sti: Remove STiH415/6 reset support
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'at91-ab-4.10-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/drivers

Drivers for 4.10:

 - few fixes for the memory drivers
 - minimal security module driver
 - support for the Secure SRAM

* tag 'at91-ab-4.10-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
  misc: sram: add Atmel securam support
  misc: sram: document new compatible
  ARM: at91: add secumod register definitions
  Documentation: dt: atmel-at91: Document secumod bindings
  memory: atmel-sdramc: use builtin_platform_driver to simplify the code
  memory: atmel-ebi: fix return value check in at91_ebi_dev_disable()
Signed-off-by: NOlof Johansson <olof@lixom.net>

This driver uses the services provided by the BPMP firmware driver to
implement a reset driver based on the MRQ_RESET request.
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The BPMP implements some services which must be represented by separate
nodes. For example, it can provide access to certain I2C controllers,
and the I2C bindings represent each I2C controller as a device tree
node. Update the binding to describe how the BPMP supports this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: renamed bpmp-i2c to i2c as per Rob]
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra186 BPMP is also a provider of power domains. Enhance the
device tree binding to describe this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Boot and Power Management Processor (BPMP) is a co-processor found
on Tegra SoCs. It is designed to handle the early stages of the boot
process and offload power management tasks (such as clocks, resets,
powergates, ...) as well as system control services.

Compared to the ARM SCPI, the services provided by BPMP are message-
based rather than method-based. The BPMP firmware driver provides the
services to transmit data to and receive data from the BPMP. Users can
also register a Message ReQuest (MRQ), for which a service routine will
be run when a corresponding event is received from the firmware.

A set of messages, called the BPMP ABI, are specified for a number of
different services provided by the BPMP (such as clocks or resets).

Based on work by Sivaram Nair <sivaramn@nvidia.com> and Joseph Lo
<josephl@nvidia.com>.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Inter-VM communication (IVC) is a communication protocol which is
designed for interprocessor communication (IPC) or the communication
between the hypervisor and the virtual machine with a guest OS.

Message channels are used to communicate between processors. They are
backed by DRAM or SRAM, so care must be taken to maintain coherence of
data.

The IVC library maintains memory-based descriptors for the transmission
and reception channels as well as the data coherence of the counter and
payload. Clients, such as the driver for the BPMP firmware, can use the
library to exchange messages with remote processors.

Based on work by Peter Newman <pnewman@nvidia.com> and Joseph Lo
<josephl@nvidia.com>.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Boot and Power Management Processor (BPMP) is a co-processor found
in Tegra SoCs. It is designed to handle the early stages of the boot
process as well as to offload power management tasks (such as clocks,
resets, powergates, ...).

The binding document defines the resources that are used by the BPMP
firmware, which implements the interprocessor communication (IPC)
between the CPU and the BPMP.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

We have to use the _safe version of list_for_each() because we're
freeing the pointer as we go along.  (This might not show up testing
depending on what config options you have enabled).

Fixes: 0fe88461 ("mailbox: Add Tegra HSP driver")
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This driver exposes a mailbox interface for interprocessor communication
using the Hardware Synchronization Primitives (HSP) module's doorbell
mechanism. There are multiple HSP instances and they provide additional
features such as shared mailboxes, shared and arbitrated semaphores.

A driver for a remote processor can use the mailbox client provided by
the HSP driver and build an IPC protocol on top of this synchronization
mechanism.

Based on work by Joseph Lo <josephl@nvidia.com>.
Acked-by: NJassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

- prepare mtk-scpsys to for multi soc support
- add support for mt2701 to mtk-scpsys

* tag 'v4.9-next-soc' of https://github.com/mbgg/linux-mediatek:
  soc: mediatek: Add MT2701 scpsys driver
  soc: mediatek: Refine scpsys to support multiple platform
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'davinci-for-v4.10/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers

This pull request adds two new drivers for better
support for LCD found on DaVinci DA8xx devices.

They allow configuration of memory interface and
bus priorities on the SoC to allow sufficient
bandwidth for the LCD and prevent underruns.

The DT bindings have been reviewed by Rob and
patches have been reviewed by Kevin.

* tag 'davinci-for-v4.10/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  bus: davinci: add support for da8xx bus master priority control
  memory: davinci: add support for da8xx DDR2/mDDR controller
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'qcom-drivers-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers

Qualcomm ARM Based Driver Updates for v4.10

* Fixup QCOM SCM to use devm_reset_controller_register
* Add QCOM pinctrl to Qualcomm MAINTAINERS entry
* Add PM8994 regulator definitions
* Add stub for WCNSS_CTRL API

* tag 'qcom-drivers-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  firmware: qcom: scm: Use devm_reset_controller_register()
  MAINTAINERS: add drivers/pinctrl/qcom to ARM/QUALCOMM SUPPORT
  pinctrl: pm8994: add pad voltage regulator defines
  soc: qcom: wcnss_ctrl: Stub wcnss_ctrl API
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'v4.10-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers

Changes to the power-domain driver including counter presets now being set
by firmware on the rk3399, avoiding infite loops when powering on/off a
domain and actually returning an error if power-domain addition fails.
The last part requires usage of the (new in 4.9-rc1) pm_genpd_remove
functionality as well.

* tag 'v4.10-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  soc: rockchip: power-domain: Handle errors from of_genpd_add_provider_onecell
  soc: rockchip: power-domain: use pm_genpd_remove in error cleanup
  soc: rockchip: power-domain: avoid infinite loop
  soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down counts
Signed-off-by: NOlof Johansson <olof@lixom.net>

The Generic Memory Interface bus can be used to connect high-speed
devices such as NOR flash, FPGAs, DSPs...
Signed-off-by: NMirza Krak <mirza.krak@gmail.com>
Tested-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: NJon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: symmetry and coding style OCD]
Signed-off-by: NThierry Reding <treding@nvidia.com>

Document the devicetree bindings for the Generic Memory Interface (GMI)
bus driver found on Tegra SOCs.
Signed-off-by: NMirza Krak <mirza.krak@gmail.com>
Tested-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add DT binding for the Hardware Synchronization Primitives (HSP). The
HSP is designed for the processors to share resources and communicate
with one another. A set of hardware synchronization primitives for
interprocessor communication (IPC) is provided. IPC protocols can use
use these hardware synchronization primitives when operating between
processors in an AMP configuration.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The various error messages refer to the PM domains as "power domain",
"genpd" and "PM domain". That's confusing, so convert all error messages
to use the most prominent: "PM domain".
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Commit 3fe57710 ("PM / Domains: Add support for removing PM
domains") add support for removing PM domains. Update the Tegra PMC
driver to remove PM domains if we fail to add a provider for the PM
domain.

Please note that the code under 'power_on_cleanup' label does not
really belong in the clean-up error path for tegra_powergate_add().
To keep the error path simple, remove this label and move the
associated code to where it needs to be invoked.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Commit 7eb231c3 ("PM / Domains: Convert pm_genpd_init() to return
an error code") updated pm_genpd_init() to return an error code. Update
the Tegra PMC driver to check the return value from pm_genpd_init() and
handle any errors returned.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: use pr_err() instead of dev_err()]
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use pr_err() instead of dev_err() when the pmc->dev field has not been
initialized yet and add a few missing error messages as well as remove
duplicate ones.

Based on work by Jon Hunter <jonathanh@nvidia.com>.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The function tegra_io_rail_prepare() converts the IO rail ID into a
bit position that is used to check the status and control the IO rail
in the PMC registers. However, rather than converting to a bit position
it is more useful to convert to a bit-mask because this is what is
actually used. By doing so the BIT() marco only needs to be used once
and we can use the IO_DPD_REQ_CODE_MASK when checking for erroneous rail
IDs.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
[treding@nvidia.com: rebase and rename bit -> mask]
Signed-off-by: NThierry Reding <treding@nvidia.com>

It is possible for the public functions, tegra_io_rail_power_on/off()
to be called before the PMC device has been probed. If this happens
then the pmc->clk member will not be initialised and the call to
clk_get_rate() in tegra_io_rail_prepare() will return zero and lead
to a divide-by-zero exception. The function clk_get_rate() will return
zero if a NULl clk pointer is passed. Therefore, rather that checking
if pmc->clk is initialised, fix this by checking the return value for
clk_get_rate() to make sure it is not zero.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such
pad can be used to control the common voltage signal level and power
state of the pins in the given pad.

I/O pads can be powered down even if the system is active, which can
save power from that I/O interface. For SoC generations prior to
Tegra124 the I/O pad voltage is automatically detected and hence the
system software doesn't need to configure it. However, starting with
Tegra210 the detection logic has been removed, so explicit control of
the I/O pad voltage by system software is required.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Bit definitions are sorted in decreasing order by offset. Apply the same
ordering to all definitions.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The function tegra_pmc_readl() returns the u32 type data and hence
change the data type of variable where this data is stored to u32
type.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use BIT macro for register field definition and make constant as U
when using in shift operator like (3 << 30) to (3U << 30)
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra186 features a combination of Denver and Cortex-A57 CPU cores
and a GPU based on the Pascal architecture. It contains an ADSP with a
Cortex-A9 CPU used for audio processing, hardware video encoders and
decoders with multi-format support, ISP for image capture processing
and BPMP for power management.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Create the driver for the da8xx master peripheral priority
configuration and implement support for writing to the three
Master Priority registers on da850 SoCs.
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: subject line adjustment]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Create a new driver for the da8xx DDR2/mDDR controller and implement
support for writing to the Peripheral Bus Burst Priority Register.
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: subject line adjustment]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Some SoCs (for example Amlogic GXBB) implement a reset controller which
only supports a reset pulse (triggered via reset_control_reset). At the
same time multiple devices (in case of the Amlogic GXBB SoC both USB
PHYs) are sharing the same reset line.

This patch allows using reset_control_reset also for shared resets.
There are limitations though:
reset_control_reset can only be used if reset_control_assert was not
used yet.
reset_control_assert can only be used if reset_control_reset was not
used yet.
For shared resets the reset is only triggered once for the lifetime of
the reset_control instance (the reset can be triggered again if all
consumers of that specific reset_control are gone, as the reset
framework will free the reset_control instance in that case).
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>

Use devm_reset_controller_register() for the reset controller
registration and fixes the memory leak when unload the module.
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>