1. 15 6月, 2010 1 次提交
  2. 03 6月, 2010 2 次提交
    • L
    • L
      ath9k_hw: add support for the AR9003 2.2 · 7284635d
      Luis R. Rodriguez 提交于
      The checksums of the initvals are:
      
      initvals -f ar9003-2p2
      0x00000000c2bfa7d5        ar9300_2p2_radio_postamble
      0x00000000ada2b114        ar9300Modes_lowest_ob_db_tx_gain_table_2p2
      0x00000000e0bc2c84        ar9300Modes_fast_clock_2p2
      0x00000000056eaf74        ar9300_2p2_radio_core
      0x0000000000000000        ar9300Common_rx_gain_table_merlin_2p2
      0x0000000078658fb5        ar9300_2p2_mac_postamble
      0x0000000023235333        ar9300_2p2_soc_postamble
      0x0000000054d41904        ar9200_merlin_2p2_radio_core
      0x000000008475a084        ar9300_2p2_baseband_postamble
      0x000000009aaafd90        ar9300_2p2_baseband_core
      0x000000003df9a326        ar9300Modes_high_power_tx_gain_table_2p2
      0x000000001cfba124        ar9300Modes_high_ob_db_tx_gain_table_2p2
      0x0000000011302700        ar9300Common_rx_gain_table_2p2
      0x00000000a9a2b114        ar9300Modes_low_ob_db_tx_gain_table_2p2
      0x00000000a9d66d40        ar9300_2p2_mac_core
      0x000000001e1d0800        ar9300Common_wo_xlna_rx_gain_table_2p2
      0x00000000a0c531c8        ar9300_2p2_soc_preamble
      0x00000000292e2544        ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
      0x000000002d3e2544        ar9300PciePhy_clkreq_enable_L1_2p2
      0x00000000293e2544        ar9300PciePhy_clkreq_disable_L1_2p2
      Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      7284635d
  3. 17 4月, 2010 4 次提交