- 29 1月, 2013 29 次提交
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由 Lucas Stach 提交于
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: NLucas Stach <dev@lynxeye.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Enable Tegra based keyboard interfacing for keys and provide all key mapping through DTS file. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Enable Tegra based keyboard controller and populate the key mapping for Whistler. With this patch, HOME, BACK, POWER and MENU keys will work. Still other keys which are in ROW3 and ROW4 will not work as it conflicts with KBC pins on SDIO2 pinmux. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
UARTC is used for the interfacing with bluetooth device. Register this UART channel as high speed serial channel so that it can use the APB DMA for data transfer. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Enable Tegra based keyboard controller and populate the key matrix for seaboard. The key matrix was originally on driver code which is removed to have clean driver. The key mapping is now passed through dts file. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: added clocks property] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
This ensures nodes are sorted in order of reg address. This makes it easier to compare against e.g. the U-Boot device trees, and is simply consistent and clean. While we're at it, remove the unit address from the cache-controller node name, since it's unique without it. Reported-by: NAllen Martin <amartin@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Lucas Stach 提交于
Add default entry for the AC97 host controller. Signed-off-by: NLucas Stach <dev@lynxeye.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Bryan Wu 提交于
This patch adds support for Tegra30 Beaver board in upstream kernel. Beaver board is a Tegra30 SoC based development board, it has following features: - T30 or T33 SoC (Qual core ARM Cortex A9) - 2 GB DDR3L - 16 GB EMMC - 1 SD slot - 1 USB Standart A port and 1 USB micro AB port - PCI-E Gig Ethernet - Audio input/output - SATA port - HDMI output - UART and JTAG Signed-off-by: NBryan Wu <pengw@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
... and disable tri-state from the pingroup that contains the poweroff GPIO. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Bryan Wu 提交于
Use engineering name 'Tegra20' instead of 'Tegra2' Signed-off-by: NBryan Wu <pengw@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
tegra30 gpio controller is not compatible with the tegra20 due to their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30 bank stride is 0x100. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: fixed typo syntax error] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Hiroshi Doyu 提交于
Add a new evaluation board, Pluto for Tegra 114 family. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Hiroshi Doyu 提交于
Add a new evaluation board, Dalmore for Tegra 114 family. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Hiroshi Doyu 提交于
Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
The patch to add USB PHY nodes to device tree was written before Tegra supported the clocks property in device tree. Now that it does, add the required clocks properties to these nodes. This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced by clk_get(phy->dev, clock_name), as part of converting the PHY driver to a platform driver. Acked-by: NVenu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Venu Byravarasu 提交于
Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Venu Byravarasu 提交于
As Tegra USB host driver is using instance number for resetting PORT0 twice, adding a new DT property for handling this. Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com> Acked-by: NAlan Stern <stern@rowland.harvard.edu> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Prashant Gaikwad 提交于
Add clock i2c clock information to device node. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Prashant Gaikwad 提交于
Add clock information to device nodes. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> [swarren: added second clock to 3d node] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Prashant Gaikwad 提交于
Add clock information to device nodes. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Prashant Gaikwad 提交于
The device tree binding models Tegra30 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> [swarren: fixed typo in binding doc] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
The Tegra20 CAR (Clock And Reset) Controller controls most aspects of most clocks within Tegra20. The device tree binding models this as a single monolithic clock provider, which exports many clocks. This reduces the number of nodes needed in device tree to represent these clocks. This binding is only useful for Tegra20; the set of clocks that exists on Tegra30 is sufficiently different to merit its own binding. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org> [pgaikwad: Added mux clk ids and sorted CAR node] Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Hiroshi Doyu 提交于
Add CPU node for Tegra30. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Hiroshi Doyu 提交于
Add CPU node for Tegra20. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 08 1月, 2013 4 次提交
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由 Rob Herring 提交于
With the addition of commit a0ae0240 (ARM: kernel: add device tree init map function), the cpu reg values must match the cpu mpidr register or we'll get warnings. For some reason, the CLUSTERID on highbank is 9, so the reg value needs to be 0x90n to quiet the warnings. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Rob Herring 提交于
While device_type is considered deprecated, it is still needed for tools like lshw to identify cpu nodes. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Marek Vasut 提交于
The second FlexCAN port uses different clock than the first one, configure correct clock to prevent hanging of the system during bringing up of the port. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sebastian Hesselbarth 提交于
During merge of the mvebu patches a clock gate for pinctrl was lost. This patch just readds the clock gate. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 07 1月, 2013 7 次提交
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由 Andrew Lunn 提交于
The Armada XP MV78230 DT include file is missing a ; at the end of the cpu node. Reported-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
We originally thought that the MV78230 variant of the Armada XP had four Ethernet interfaces, like the other variants MV78260 and MV78460. In fact, this is not true, and the MV78230 has only three Ethernet interfaces. So, the definitions of the Ethernet interfaces is now done as follows: * armada-370-xp.dtsi: definitions of the first two interfaces, that are common to Armada 370 and Armada XP * armada-xp.dtsi: definition of the third interface, common to all Armada XP variants. * armada-xp-mv78260.dtsi and armada-xp-mv78460.dtsi: definition of the fourth interface. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
Contrary to our understanding at the time armada-xp-mv78230.dtsi was written, the MV78230 variant of the Armada XP SoC has two cores and not one. This patch updates the .dtsi file to take into account this reality. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Andrew Lunn 提交于
With the change to a DT based pinctrl/gpio driver, using gpio API calls in board-*.c files no longer works, a dereferenced NULL pointer exception occurs instead. By converting the GPIO code into a fixed-regulator which gets probed later once pinctrl/gpio is available, we avoid the exception. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NStefan Peter <s.peter@mplch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Nobuhiro Iwamatsu 提交于
Clock Management of kirkwood has moved to DT clock providers. However, TWSI1 has not yet been done. This switches TWSI1 of 88f6282 to DT clock providers. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Andrew Lunn 提交于
Without the clock being held by a driver, it gets turned off at a bad time causing the SoC to lockup. This is often during reboot. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NStefan Peter <s.peter@mpl.ch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Gregory CLEMENT 提交于
The UART controller used in the Armada 370 and Armada XP SoCs is the Synopsys DesignWare 8250 (aka Synopsys DesignWare ABP UART). The improper use of the ns16550 can lead to a kernel oops during boot if a character is sent to the UART before the initialization of the driver. The DW APB has an extra interrupt that gets raised when writing to the LCR when busy. This explains why we need to use dw-apb-uart driver to handle this. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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