1. 02 1月, 2010 1 次提交
    • M
      sh: Correct the PTRS_PER_PMD and PMD_SHIFT values · 3f5ab768
      Matt Fleming 提交于
      The previous expressions were wrong which made free_pmd_range() explode
      when using anything other than 4KB pages (which is why 8KB and 64KB
      pages were disabled with the 3-level page table layout).
      
      The problem was that pmd_offset() was returning an index of non-zero
      when it should have been returning 0. This non-zero offset was used to
      calculate the address of the pmd table to free in free_pmd_range(),
      which ended up trying to free an object that was not aligned on a page
      boundary.
      
      Now 3-level page tables should work with 4KB, 8KB and 64KB pages.
      Signed-off-by: NMatt Fleming <matt@console-pimps.org>
      3f5ab768
  2. 17 12月, 2009 1 次提交
    • M
      sh: Definitions for 3-level page table layout · 5d9b4b19
      Matt Fleming 提交于
      If using 64-bit PTEs and 4K pages then each page table has 512 entries
      (as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows
      the convention that all structures in the page table (pgd_t, pmd_t,
      pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require
      64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs
      it is only possible to map 1GB of virtual address space.
      
      In order to map all 4GB of virtual address space we need to adopt a
      3-level page table layout. This actually works out better for
      CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2
      areas (which are untranslated) instead of 256.
      Signed-off-by: NMatt Fleming <matt@console-pimps.org>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      5d9b4b19