Previously dbi accessors can be used to access data of size 4 bytes. But
there might be situations (like accessing MSI_MESSAGE_CONTROL in order to
set/get the number of required MSI interrupts in EP mode) where dbi
accessors must be used to access data of size 2. This is in preparation
for adding endpoint mode support to designware driver.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NNiklas Cassel <niklas.cassel@axis.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Joao Pinto <Joao.Pinto@synopsys.com>

dwc has 2 dbi address space labeled dbics and dbics2. The existing helper
to access dbi address space can access only dbics. However dbics2 has to
be accessed for programming the BAR registers in the case of EP mode. This
is in preparation for adding EP mode support to dwc driver.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NNiklas Cassel <niklas.cassel@axis.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Joao Pinto <Joao.Pinto@synopsys.com>

Even when using the PHY framework, we need the elbi_base.  Before this
patch, we didn't initialize elbi_base, which caused NULL pointer
dereferences later.

Fixes: e7cd7ef5 ("PCI: exynos: Support the PHY generic framework")
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Fix the following crash, seen in dwc/pci-imx6.

  Unable to handle kernel NULL pointer dereference at virtual address 00000070
  pgd = c0004000
  [00000070] *pgd=00000000
  Internal error: Oops: 805 [#1] SMP ARM
  Modules linked in:
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.10.0-09686-g9e314890 #1
  Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
  task: cb850000 task.stack: cb84e000
  PC is at imx6_pcie_probe+0x2f4/0x414
  ...

While at it, fix the same problem in various drivers instead of waiting for
individual crash reports.

The change in the imx6 driver was tested with qemu. The changes in other
drivers are based on code inspection and have been compile tested only.

Fixes: 442ec4c0 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures")
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>  # designware-plat
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>

Keep only the host-specific members in struct pcie_port and move the common
members (i.e common to both host and endpoint) to struct dw_pcie.  This is
in preparation for adding endpoint mode support to designware driver.

While at that also fix checkpatch warnings.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Richard Zhu <hongxing.zhu@nxp.com>
CC: Lucas Stach <l.stach@pengutronix.de>
CC: Murali Karicheri <m-karicheri2@ti.com>
CC: Minghuan Lian <minghuan.Lian@freescale.com>
CC: Mingkai Hu <mingkai.hu@freescale.com>
CC: Roy Zang <tie-fei.zang@freescale.com>
CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
CC: Niklas Cassel <niklas.cassel@axis.com>
CC: Jesper Nilsson <jesper.nilsson@axis.com>
CC: Joao Pinto <Joao.Pinto@synopsys.com>
CC: Zhou Wang <wangzhou1@hisilicon.com>
CC: Gabriele Paoloni <gabriele.paoloni@huawei.com>
CC: Stanimir Varbanov <svarbanov@mm-sol.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>

No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do
anything specific to access configuration space. It can be just renamed to
dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-By: NJoao Pinto <jpinto@synopsys.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Murali Karicheri <m-karicheri2@ti.com>
CC: Stanimir Varbanov <svarbanov@mm-sol.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>

Add platform_set_drvdata() in all designware-based drivers to store the
private data structure of the driver so that dev_set_drvdata() can be used
to get back private data structure in add_pcie_port/host_init.  This is in
preparation for splitting struct pcie_port into core and host only
structures. After the split pcie_port will not be part of the driver's
private data structure and *container_of* used now to get the private data
pointer cannot be used.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Richard Zhu <hongxing.zhu@nxp.com>
CC: Lucas Stach <l.stach@pengutronix.de>
CC: Murali Karicheri <m-karicheri2@ti.com>
CC: Minghuan Lian <minghuan.Lian@freescale.com>
CC: Mingkai Hu <mingkai.hu@freescale.com>
CC: Roy Zang <tie-fei.zang@freescale.com>
CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
CC: Niklas Cassel <niklas.cassel@axis.com>
CC: Jesper Nilsson <jesper.nilsson@axis.com>
CC: Joao Pinto <Joao.Pinto@synopsys.com>
CC: Zhou Wang <wangzhou1@hisilicon.com>
CC: Gabriele Paoloni <gabriele.paoloni@huawei.com>
CC: Stanimir Varbanov <svarbanov@mm-sol.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>

Group all the PCI drivers that use DesignWare core in dwc directory.
dwc IP is capable of operating in both host mode and device mode and
keeping it inside the *host* directory is misleading.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jingoohan1@gmail.com>
Acked-By: NJoao Pinto <jpinto@synopsys.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Minghuan Lian <minghuan.Lian@freescale.com>
Cc: Mingkai Hu <mingkai.hu@freescale.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Niklas Cassel <niklas.cassel@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>

Switch the pci-exynos driver to generic PHY framework.  At the same time
backward compatibility is preserved: Warning will be printed for old DTB.

Refer to the binding file:
- Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: NAlim Akhtar <alim.akhtar@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NJingoo Han <jingoohan1@gmail.com>

Currently the Exynos PCIe driver only supports the Exynos5440 SoC.
Refactor the driver to allow support for other Exynos SoC.

Following are the main changes in this patch:

1) Add separate structs for memory, clock resources

  Future Exynos SoC will have different hardware resources such as iomem,
  clocks, regmap handles, etc., so keeping these resources in separate
  structs will let us initialize them via per-SoC ops and avoid littering
  the code with of_machine_is_compatible().

2) Add exynos_pcie_ops struct which will allow us to support the
   differences in resources in different Exynos SoC.

No functional change intended.
Signed-off-by: NNiyas Ahmed S T <niyas.ahmed@samsung.com>
Signed-off-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: NAlim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NJingoo Han <jingoohan1@gmail.com>

Remove duplicated register reads and writes.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NJingoo Han <jingoohan1@gmail.com>

Use the bitops BIT() macro to build bitmasks.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NJingoo Han <jingoohan1@gmail.com>

Remove unnecessary local variables: elbi_base, phy_base, block_base.  We
need one resource structure for assigning each resource.  Reuse the single
'res' variable for all.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NJingoo Han <jingoohan1@gmail.com>

There is no reason to maintain *_blk/phy/elbi_* as register accessors.
They can be replaced by one accessor to make maintenance easier.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NJingoo Han <jingoohan1@gmail.com>

Rename the simple pointer name as "ep" instead of "exynos_pcie".  After
applying this patch, it can save the 10 characthers within one line.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NJingoo Han <jingoohan1@gmail.com>

Reorder struct exynos_pcie to put generic fields first.  No functional
change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Most struct exynos_pcie pointers are already called "exynos_pcie".  Change
the rest of them to match.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The register accessors are not performance critical and are small enough
that the compiler can inline them itself if it makes sense.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Use a local "struct device *dev" for brevity and consistency with other
drivers.  No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers.  No functional
change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers
allow a driver to override the default DesignWare register accessors.

Make the signature of the override functions the same as the default
accessors.  This makes the default dw_pcie_readl_rc() and the corresponding
override more structurally similar: both will compute the final register
address with "pp->dbi_base + reg".  Previously dw_pcie_readl_rc() computed
the address and passed it to the override.

No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

This code is not being built as a module by anyone:

  drivers/pci/host/Kconfig:config PCI_EXYNOS
  drivers/pci/host/Kconfig:  bool "Samsung Exynos PCIe controller"

Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(),
etc., so that when reading the driver there is no doubt it is builtin-only.
The information is preserved in comments at the top of the file.

Note that for non-modular code, MODULE_DEVICE_TABLE is a no-op.

[bhelgaas: changelog]
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Kukjin Kim <kgene@kernel.org>

dw_pcie_readl_rc() reads a u32 value.  Previously we stored that value in
space supplied by the caller.  Return the u32 value directly instead.

This makes the calling code read better and makes it obvious that the
caller need not initialize the storage.  In the following example it isn't
clear whether "val" is initialized before being used:

  dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
  if (val & PCI_COMMAND_MEMORY)
    ...

No functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.

Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.

Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.

[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: NJoao Pinto <jpinto@synopsys.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NPratyush Anand <pratyush.anand@gmail.com>

On -RT and if kernel is booting with "threadirqs" cmd line parameter,
PCIe/PCI (MSI) IRQ cascade handlers (like dra7xx_pcie_msi_irq_handler())
will be forced threaded and, as result, will generate warnings like this:

  WARNING: CPU: 1 PID: 82 at kernel/irq/handle.c:150 handle_irq_event_percpu+0x14c/0x174()
  irq 460 handler irq_default_primary_handler+0x0/0x14 enabled interrupts
  Backtrace:
   (warn_slowpath_common) from (warn_slowpath_fmt+0x38/0x40)
   (warn_slowpath_fmt) from (handle_irq_event_percpu+0x14c/0x174)
   (handle_irq_event_percpu) from (handle_irq_event+0x84/0xb8)
   (handle_irq_event) from (handle_simple_irq+0x90/0x118)
   (handle_simple_irq) from (generic_handle_irq+0x30/0x44)
   (generic_handle_irq) from (dra7xx_pcie_msi_irq_handler+0x7c/0x8c)
   (dra7xx_pcie_msi_irq_handler) from (irq_forced_thread_fn+0x28/0x5c)
   (irq_forced_thread_fn) from (irq_thread+0x128/0x204)

This happens because all of them invoke generic_handle_irq() from the
requested handler.  generic_handle_irq() grabs raw_locks and thus needs to
run in raw-IRQ context.

This issue was originally reproduced on TI dra7-evem, but, as was
identified during discussion [1], other hosts can also suffer from this
issue.  Fix all them at once by marking PCIe/PCI (MSI) IRQ cascade handlers
IRQF_NO_THREAD explicitly.

[1] http://lkml.kernel.org/r/1448027966-21610-1-git-send-email-grygorii.strashko@ti.com

[bhelgaas: add stable tag, fix typos]
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de> (for imx6)
CC: stable@vger.kernel.org
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Kukjin Kim <kgene@kernel.org>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Richard Zhu <Richard.Zhu@freescale.com>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: Simon Horman <horms@verge.net.au>
CC: Pratyush Anand <pratyush.anand@gmail.com>
CC: Michal Simek <michal.simek@xilinx.com>
CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
CC: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to
split the address into "addr" and "where".  The callees assumed "addr" was
32-bit aligned (with zeros in the low two bits) and they used only the low
two bits of "where".

Accept the entire address in "addr" and drop the now-redundant "where"
argument.  As an example, this replaces this:

  int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
    *val = readb(addr + (where & 1));

with this:

  int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
    *val = readb(addr):

[bhelgaas: changelog, split access size change to separate patch]
Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

All the DesignWare-based host drivers loop waiting for the link to come up,
but they do it several ways that are needlessly different.

Wait for the link to come up in a consistent style across all the
DesignWare drivers.  No functional change.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NPratyush Anand <pratyush.anand@gmail.com>

Use a semicolon, not a comma, to terminate a statement.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

This patch fixes the following checkpatch warning:

  WARNING: void function return statements are not generally useful
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The add_pcie_port() and pcie_init() functions are Exynos-specific.  Add
exynos prefix to avoid collision in global name space.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

A platform_driver does not need to set an owner, it will be populated by the
driver core.
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

On i.MX6 the host controller MSI IRQ is shared with PCI legacy INTD.  Make
sure we don't bail too early from the IRQ handler.

The issue is fairly theoretical as it would require a system setup with a
PCIe switch where one connected device is using legacy INTD and another one
using MSI, but better fix it now.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NRichard Zhu <r65037@freescale.com>

add_pcie_port() is called only from exynos_pcie_probe(), which is annotated
with __init.  Thus it makes sense to annotate add_pcie_port() with __init
to avoid the following section mismatch warning:

  WARNING: drivers/pci/built-in.o(.text.unlikely+0xf8): Section mismatch in reference from the function add_pcie_port() to the function .init.text:dw_pcie_host_init()
    The function add_pcie_port() references
    the function __init dw_pcie_host_init().
    This is often because add_pcie_port lacks a __init
    annotation or the annotation of dw_pcie_host_init is wrong.

[bhelgaas: changelog]
Reported-by: Nkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>

The site-specific OOM messages are unnecessary, because they duplicate the
MM subsystem generic OOM message.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Serialization of configuration accesses is provided by 'pci_lock' in
drivers/pci/access.c thus making the driver's 'conf_lock' superfluous.
Signed-off-by: NAndrew Murray <amurray@embedded-bits.co.uk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NRichard Zhu <r65037@freescale.com>

The cfg_read/write functions are DesignWare-specific.  Add dw_pcie prefix
to avoid collision in global name space.
Tested-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>

This driver is DT only.  Hence of_match_ptr is not required.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>

Add the missing clk_disable_unprepare() before return
from exynos_pcie_probe() in the error handling case.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>

When link failed, there is no need to turn on phy block. Also,
turning on phy block is added, in order to turn on phy block
regardless of the default value of phy registers.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>