These smp_operations structures are not over-written, so add "const"
qualifier and replace __initdata with __initconst.

Also, add "static" where it is possible.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NMoritz Fischer <moritz.fischer@ettus.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org> # qcom part
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NWei Xu <xuwei5@hisilicon.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Acked-by: NNicolas Pitre <nico@linaro.org>
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch adds suspend function for i.MX6UL, it supports
"standby" and "mem" mode, for "standby" mode, SoC will
enter STOP mode only, while for "mem" mode, SoC will
enter STOP mode and DDR IO will be set to low power
mode.

As i.MX6UL contains a "Cortex-A7" ARM core which has no
PL310, so we need to avoid any PL310 operations during
suspend/resume, also, we need to flush Cortex-A7's inernal
L2 cache before suspend.
Signed-off-by: NAnson Huang <b20788@freescale.com>

In order to save power the DDR pins should be put into high
impedance when in suspend to RAM.

This requires manually requesting self refresh (rather than using the
automatic mode implemented by the CCM / ESDCTL), followed by
reconfiguring the IOMUXC.

Of course the code to do this cannot itself run from DDR so the
code is copied to and executed from internal memory.

In my tests using a custom i.MX53 board with LPDDR2 RAM
this reduced the suspend power consumption from 200mW to 60mW.
Signed-off-by: NMartin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Removed the duplicated function declaration of mxc_timer_init
which was already declared in drivers/clk/imx/clk.h.
Signed-off-by: NShenwei Wang <shenwei.wang@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function")
moves imx6_set_lpm() from clock init function into
imx6_pm_common_init().  This causes a hang when cpuidle support is
enabled.  The reason for that is ARM core clock is shut down
unexpectedly by WAIT mode.  It happens with the following call stack:

    cpuidle_register_governor()
        cpuidle_switch_governor()
            cpuidle_uninstall_idle_handler()
                synchronize_sched()
                    wait_rcu_gp()
                        wait_for_completion()

When wait_for_completion() is called as above, all cores are idle/WFI.
Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a
hardware shutdown of the ARM core clock.

To fix the regression, we need to ensure that CCM_CLPCR_LPM is
initialized into RUN mode earlier than cpuidle governor registration,
which is a postcore_initcall.  This patch creates function
imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into
RUN mode, and have the function called from machine .init_irq hook,
which should be early enough.
Reported-by: NKevin Hilman <khilman@kernel.org>
Fixes: 8fb76a07 ("ARM: imx6: set initial power mode in pm function")
Tested-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NTyler Baker <tyler.baker@linaro.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We are about to move imx6 clock driver into drivers/clk, so let's get
imx6 pm code map CCM block on its own rather than relying on clock
driver to do the mapping.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Rather than setting initial low-power mode in every single i.MX6 clock
initialization function, we should really do that in pm code.  Let's
move imx6q_set_lpm(WAIT_CLOCKED) call into imx6_pm_common_init().

While at it, let's rename the function to imx6_set_lpm() since it's
actually common for all i.MX6 SoCs.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We are about to move imx5 clock driver into drivers/clk, so let's get
imx5 pm code map CCM block on its own rather than relying on clock
driver to do the mapping.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The revision definitions and declarations are widely used by clock
drivers.  As a step of moving clock drivers out of arch/arm/mach-imx,
let's create header include/soc/imx/revision.h to accommodate them.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Pass physical address of timer block to mxc_timer_init() call, which in
turn does dynamic mapping within the function.  Thus, we can avoid using
static mapping in clock drivers.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Now that the GPC has been converted to be a full blown irqchip
(and not a mole on the side of the GIC), booting a new kernel
with an old DT is likely to result in a rough ride for the user.

This patch makes sure such a situation is promptly detected and
the user made aware that a DT update is in order.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.

This patch does just this, updating the DT files to actually
reflect what the HW provides.

BIG FAT WARNING: because the DTs were so far lying by not
exposing the fact that the GPC block is actually the first
interrupt controller in the chain, kernels with this patch
applied wont have any suspend-resume facility when booted
with old DTs, and old kernels with updated DTs won't even boot.
Tested-by: NStefan Agner <stefan@agner.ch>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We use dynamic memory mapping when using dt, so remove all the static mappings.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

mx25_clocks_init() is only used to register the clocks for non-dt platforms.

As mx25 has been converted to a dt-only platform, we can safely remove it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch introduces an independent cpuidle driver for
i.MX6SX, and supports arm power off in idle, totally
3 levels of cpuidle are supported as below:

1. ARM WFI;
2. SOC in WAIT mode;
3. SOC in WAIT mode + ARM power off.

ARM power off can save at least 5mW power.

This patch also replaces imx6q_enable_rbc with imx6_enable_rbc.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The imx6 PM code seems to be quite creative in its use of irq_data,
using something that is very much a hardware interrupt number where
we expect a virtual one.  Yes, it worked so far, but that's only
luck, and it will definitely explode in 3.19.

Fix it by using a pair of helper functions that deal with the
actual hardware.
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Freescale LS1021A SoCs deploy two cortex-A7 processors,
this adds bring-up support for the secondary core.
Signed-off-by: NJingchang Lu <b35083@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3,
we used cpu type to decide how to do these settings in suspend
before which is NOT flexible, take i.MX6SL for example, although
it has LPDDR2 on EVK board, but users can also use DDR3 on other
boards, so it is better to read the DDR type from MMDC then decide
how to do related settings.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

System restart mechanism has been changed with the introduction
of "kernel restart handler call chain support". The imx2 watchdog
based restart handler has been moved to the driver, and these
restart can be removed from the machine layer.

This patch cleans up the device tree version machine reset init with
mxc_arch_reset_init_dt and removes corresponding .restart handler,
for the .init_machine that can be handled by system default after
removing the mxc_arch_reset_init_dt, the .init_machine is also removed.
Signed-off-by: NJingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

With commit c716483c ("ARM: 8122/1: smp_scu: enable SCU standby
support"), the STANDBY bit of SCU is handled by core function
scu_enable().  So imx_scu_standby_enable() can be removed now.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch uses clocksource_of_init() call for DT targets.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The i.MX SoCs allow to setup fine grained access rights to peripherals on the
AIPS bus.
This is done via the Peripheral Access Register (PAR) in e.g. the i.MX21
or in later SoC versions the Off-Platform Peripheral Access Control Register
(OPACR), e.g. i.MX53.
Under certain circumstances this leads to problems in which bus masters are
not granted their access rights to peripherals.
To be able to disable these restrictions on DT platforms, add a helper function
that looks for AIPS nodes in the DT and disables them for every compatible node
it finds.
The compatible has to be declared in the mach-specific entry file, where this
helper function should then be called.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Replace .init_time() hook with of_clk_init() for DT targets.

Based on:
  d4347ee ARM: i.MX27 clk: Use of_clk_init() for DT case
Signed-off-by: NDenis Carikli <denis@eukrea.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add standby mode support for suspend, to enter standby mode:

echo standby > /sys/power/state;

Use UART or RTC alarm to wake up system, when system enters
standby mode, SOC will enter STOP mode with ARM core kept
power on and 24M XTAL on.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

According to hardware design, mem bit must be clear before
entering DSM mode, as ARM core will be power gated in DSM mode.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add suspend support for i.MX6SX.

To enter suspend, echo mem > /sys/power/state.
To exit suspend, using RTC alarm or enable debug UART wakeup.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Replace .init_time() hook with of_clk_init() for DT targets.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The mx51_display_revision() is a dead declaration.  Remove it.  Also,
move mx51_revision() into common.h.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The only code left in mm-imx5.c is to create static mapping.  While all
IMX platform code are moved to use dynamic mapping, the file can just be
removed now.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

These imx5 init_early[late] hooks are called only from mach-imx5x.c.
Let's move them into mach-imx5x.c.

While at it, replace the static mapping in imx51_ipu_mipi_setup() with
dynamic mapping.  Also this function and imx_src_init() do not
necessarily to be called at .init_early hook, so move them into
.init_machine.

The mxc_iomux_v3_init() is dropped from imx51_init_early() in the
moving, since it's only needed by non-DT boot.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The imx5 pm code uses static mapping to access Cortex and GPC registers.
The patch create struct imx5_pm_data to encode physical address of
Cortex and GPC block, and create dynamic mapping for them at run-time.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The imx5 pm code needs to access CCM registers.  Let's remove the use
of CCM static mapping in pm code by reusing the dynamic mapping created
in clock code.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The function imx51_soc_init() was used by non-DT boot only.  Since
i.MX51 supports DT only, the function can be removed now.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

After i.MX51 supports DT only, tzic_init_irq() can figure out the
tzic_base on its own.  Thus, it can directly be .init_irq hook, and
mx51[53]_init_irq() can be saved.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Since i.MX51 becomes a DT only platform, we can make mx51_clocks_init()
a DT call and save function mx51_clocks_init_dt() now.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch moves IRQ handler setup to the its corresponded IRQ
driver (AVIC, TZIC).
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Signed-off-by: NGilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The suspend-imx6.S is introduced recently for suspend low-level assembly
code.  Since function v7_cpu_resume() is only used by suspend support,
it makes sense to move the function into suspend-imx6.S, and control the
build of the file with CONFIG_SUSPEND option.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

When system enter suspend, we can set the DDR IO to
high-Z state to save DDR IOs' power consumption, this
operation can save many power(from ~26mA@1.5V to ~15mA@1.5V,
measured on i.MX6Q SabreSD board, R25) of DDR IOs. To
achieve that, we need to copy the suspend code to ocram
and run the low level hardware related code(set DDR IOs
to high-Z state) in ocram.

If there is no ocram space available, then system will
still do suspend in external DDR, hence no DDR IOs will
be set to high-Z.

The OCRAM usage layout is as below,

ocram suspend region(4K currently):
======================== high address ======================
                              .
                              .
                              .
                              ^
                              ^
                              ^
                      imx6_suspend code
             PM_INFO structure(imx6_cpu_pm_info)
======================== low address =======================
Reviewed-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add cpuidle support for i.MX6SL, currently only support
two cpuidle levels(ARM wfi and WAIT mode), and add software
workaround for WAIT mode errata as below:

ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
          during WAIT mode entry process could cause cache memory
          corruption.

Software workaround:
    To prevent this issue from occurring, software should ensure that
the ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
entering WAIT mode.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>