1. 12 2月, 2016 1 次提交
  2. 11 2月, 2016 1 次提交
  3. 29 1月, 2016 1 次提交
  4. 22 1月, 2016 2 次提交
  5. 20 1月, 2016 1 次提交
  6. 08 1月, 2016 1 次提交
  7. 30 12月, 2015 1 次提交
  8. 19 12月, 2015 1 次提交
    • D
      drivers: net: cpsw: fix RMII/RGMII mode when used with fixed-link PHY · f1eea5c1
      David Rivshin 提交于
      Commit 1f71e8c9 ("drivers: net: cpsw: Add
      support for fixed-link PHY") did not parse the "phy-mode" property in
      the case of a fixed-link PHY, leaving slave_data->phy_if with its default
      of PHY_INTERFACE_MODE_NA(0). This later gets passed to phy_connect() in
      cpsw_slave_open(), and eventually to cpsw_phy_sel() where it hits a default
      case that configures the MAC for MII mode.
      
      The user visible symptom is that while kernel log messages seem to indicate
      that the interface is set up, there is no network communication. Eventually
      a watchdog error occurs:
          NETDEV WATCHDOG: eth0 (cpsw): transmit queue 0 timed out
      
      Fixes: 1f71e8c9 ("drivers: net: cpsw: Add support for fixed-link PHY")
      Signed-off-by: NDavid Rivshin <drivshin@allworx.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f1eea5c1
  9. 18 12月, 2015 1 次提交
  10. 16 12月, 2015 3 次提交
  11. 15 12月, 2015 1 次提交
  12. 12 12月, 2015 1 次提交
  13. 11 12月, 2015 1 次提交
  14. 10 12月, 2015 1 次提交
  15. 04 12月, 2015 2 次提交
  16. 03 12月, 2015 1 次提交
    • M
      net: mvneta: enable setting custom TX IP checksum limit · 9110ee07
      Marcin Wojtas 提交于
      Since Armada 38x SoC can support IP checksum for jumbo frames only on
      a single port, it means that this feature should be enabled per-port,
      rather than for the whole SoC.
      
      This patch enables setting custom TX IP checksum limit by adding new
      optional property to the mvneta device tree node. If not used, by
      default 1600B is set for "marvell,armada-370-neta" and 9800B for other
      strings, which ensures backward compatibility. Binding documentation
      is updated accordingly.
      Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9110ee07
  17. 24 11月, 2015 1 次提交
  18. 19 11月, 2015 1 次提交
  19. 05 11月, 2015 1 次提交
  20. 30 10月, 2015 1 次提交
  21. 28 10月, 2015 1 次提交
  22. 27 10月, 2015 4 次提交
  23. 21 10月, 2015 2 次提交
  24. 17 10月, 2015 1 次提交
  25. 08 10月, 2015 1 次提交
  26. 07 10月, 2015 1 次提交
  27. 03 10月, 2015 1 次提交
  28. 22 9月, 2015 1 次提交
  29. 21 9月, 2015 1 次提交
    • H
      net: add Hisilicon Network Subsystem support (config and documents) · fc7e37c6
      huangdaode 提交于
      The Hisilicon Network Subsystem is a long term evolution IP which is
      supposed to be used in Hisilicon ICT SoC. The IP, which is called hns
      for short, is a TCP/IP acceleration engine, which can directly decode
      TCP/IP stream and distribute them to different ring buffers.
      
      HNS can be configured to work on different mode for different scenario.
      This patch make use only some of the mode to make it as standard
      ethernet NIC. The other mode will be added soon.
      
      The whole function has 4 kernel sub-modules:
      
      hnae: the HNS acceleration engine framework. It provides a abstract
      interface between the engine and the upper layers which make use of the
      engine by ring buffer.
      
      hns_enet_drv: a standard ethernet driver that base on the ring buffer.
      
      hns_dsaf: one of the implementation of HNS acceleration engine, which is
      applied on Hililicon hip05, Hi1610 and other later-on SoCs
      
      hns_mdio: the mdio control to the PHY, used by acceleration engine
      
      This submit add basic config and documents
      Signed-off-by: Nhuangdaode <huangdaode@hisilicon.com>
      Signed-off-by: NKenneth Lee <liguozhu@huawei.com>
      Signed-off-by: NYisen Zhuang <Yisen.Zhuang@huawei.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fc7e37c6
  30. 18 9月, 2015 1 次提交
  31. 16 9月, 2015 1 次提交
    • M
      drivers: net: cpsw: Add support to drive gpios for ethernet to be functional · 1d147ccb
      Mugunthan V N 提交于
      In DRA72x EVM, by default slave 1 is connected to the onboard
      phy, but slave 2 pins are also muxed with video input module
      which is controlled by pcf857x gpio and currently to select slave
      0 to connect to phy gpio hogging is used, but with
      omap2plus_defconfig the pcf857x gpio is built as module. So when
      using NFS on DRA72x EVM, board doesn't boot as gpio hogging do
      not set proper gpio state to connect slave 0 to phy as it is
      built as module and you do not see any errors for not setting
      gpio and just mentions dhcp reply not got.
      
      To solve this issue, introducing "mode-gpios" in DT when gpio
      based muxing is required. This will throw a warning when gpio
      get fails and returns probe defer. When gpio-pcf857x module is
      installed, cpsw probes again and ethernet becomes functional.
      Verified this on DRA72x with pcf as module and ramdisk.
      Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
      Acked-by: NTony Lindgren <tony@atomide.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1d147ccb
  32. 01 9月, 2015 1 次提交