Add support for framebuffer compression on GM45 and above.  Removes
some unnecessary I915_HAS_FBC checks as well (this is now part of the
FBC display function).
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

This patch splits out several of the display functions into a separate
display function table to avoid tons of chipset specific if..else
if..else if blocks all over.  There are more opportunities for this
(some noted in the structure defintition); so more cleanup patches will
follow.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

We usually don't have an SAREA, and we always want to update the FBC
status anyway, so move the update up above the various master/sarea
checks.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

A very high dotclock (e.g. 229500kHz as reported by Anton) can cause
the entries_required variable to overflow, potentially leading to a
FIFO watermark value that's too low to support the given mode.  Split
the division across the calculation to avoid this.

Cc: stable@kernel.org
Reported-by: NAnton Khirnov <wyskas@gmail.com>
Tested-by: NAnton Khirnov <wyskas@gmail.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

By handling latency variable efficiently we also get rid of this warning :

  CC [M]  drivers/gpu/drm/i915/intel_display.o
drivers/gpu/drm/i915/intel_display.c: In function ‘igd_enable_cxsr’:
drivers/gpu/drm/i915/intel_display.c:1918: warning: ‘latency’ may be used uninitialized in this function
Signed-off-by: NJaswinder Singh Rajput <jaswinderrajput@gmail.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Due to a bogus FBC support check and failing to check for FBC support
in the right places, mode setting on non-mobile platforms could fail
and hang in the FBC disable routine.  Fix it up.

This fix highlights the need for cleanups in this area (function
pointers and better feature support checks).  Patches for that to
follow.
Tested-by: NKenny Graunke <kenny@whitecape.org>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Arrandale has new window based method for panel fitting.
This one enables full screen aspect scaling on LVDS. It fixes
standard mode display failure on LVDS for Arrandale.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

New register for PCH LVDS on IGDNG should be used.
This is a copy-n-paste typo. This fixes possible dual
channel LVDS panel failure on IGDNG.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

This patch adds framebuffer compression (good for about ~0.5W power
savings in the best case) support for pre-GM45 chips.  GM45+ have a new,
more flexible FBC scheme that will be added in a separate patch.

FBC can't always be enabled: the compressed buffer must be physically
contiguous and reside in stolen space.  So if you have a large display
and a small amount of stolen memory, you may not be able to take
advantage of FBC.  In some cases, a BIOS setting controls how much
stolen space is available.  Increasing this to 8 or 16M can help.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

Some laptop platforms will disable pipes and/or planes at lid close time
and not restore them when the lid is opened again.  So catch the lid
event, and if the lid was opened, force a mode restore.

Fixes fdo bug #21230.
Acked-by: NMatthew Garrett <mjg@redhat.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

When the output device is LVDS, maybe the pixel clock of adjusted_mode will be
less than that in mode. In such case it will set the incorrect multipler factor
in DPLL_MD register.
So the dpll_md_reg will be reset when the output type is non-SDVO

https://bugs.freedesktop.org/show_bug.cgi?id=22761Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Reviewd-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NEric Anholt <eric@anholt.net>

Fixes (again) whole-system lockups due to GPU lockups.
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

It seems that on IGDNG the same swizzling setup always applys.
And front buffer tiling needs to set address swizzle in display
arb control too.

Fix plane tricle feed setting in v1 which should be disable bit,
and always setup address swizzle to let hardware care for buffer
tiling in all cases.
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NEric Anholt <eric@anholt.net>

And clean up a small whitespace goof-up in the same function, while
I was looking at it.
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NEric Anholt <eric@anholt.net>
Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>

There are several sources of unnecessary power consumption on Intel
graphics systems. The first is the LVDS clock. TFTs don't suffer from
persistence issues like CRTs, and so we can reduce the LVDS refresh rate
when the screen is idle. It will be automatically upclocked when
userspace triggers graphical activity. Beyond that, we can enable memory
self refresh. This allows the memory to go into a lower power state when
the graphics are idle. Finally, we can drop some clocks on the gpu
itself. All of these things can be reenabled between frames when GPU
activity is triggered, and so there should be no user visible graphical
changes.
Signed-off-by: NJesse Barnes <jesse.barnes@intel.com>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Some i915/i945 platforms have a fairly high memory latency in certain
situations, so increase our constant a bit to avoid FIFO underruns.
The effect should be positive on other platforms as well; we'll have a
bit more insurance against a busy memory subsystem due to the extra
FIFO entries.

Fixes fdo bug #23368.  Needed for 2.6.31.
Tested-by: NSven Arvidsson <sa@whiz.se>
Tested-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

Initially I always meant this code to be shared, but things
ran away from me before I got to it.

This refactors the i915 and radeon kms fbdev interaction layers
out into generic helpers + driver specific pieces.

It moves all the panic/sysrq enhancements to the core file,
and stores a linked list of kernel fbs. This could possibly be
improved to only store the fb which has fbcon on it for panics
etc.

radeon retains some specific codes used for a big endian
workaround.

changes:
fix oops in v1
fix freeing path for crtc_info
Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Based on Bspec each encoder has different sharing pipe property,
i.e. Integrated or SDVO TV both will occupy one pipe exclusively,
and sdvo-non-tv and crt are allowed to share one. The patch moves
sharing judgment into differnet output functions, and sets the right
clone bit.

This fixes both HDMI outputs choosing the same pipe.

https://bugs.freedesktop.org/show_bug.cgi?id=22247Signed-off-by: NMa Ling <ling.ma@intel.com>
Reviewed-by : Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

After the following commit is shipped, the SDVO C detection will depend on
the SDVO_C/DP detion bit.
commit 13520b05
Author: Kristian Høgsberg <krh@redhat.com>
Date:   Fri Mar 13 15:42:14 2009 -0400

    drm/i915: Read the right SDVO register when detecting SVDO/HDMI.

According to the spec we should continue to detect the SDVO_B/C based on
the SDVO_B detection bit.  The new detection bit on G4X platform is for
the HDMI_C detection rather than SDVO_C detection.

https://bugs.freedesktop.org/show_bug.cgi?id=20639Signed-off-by: NMa Ling <ling.ma@intel.com>
Acked-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Commit 0c2e3952 is not sufficient to
get fd.o bug #20115 fixed.
In addition intel_find_best_PLL() must not only rely on BIOS settings
for i9xx chips but also for i8xx, so drop the IS_I9XX() check.
Signed-off-by: NBruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

http://bugs.freedesktop.org/show_bug.cgi?id=21417Signed-off-by: NSean Young <sean@mess.org>
Reviewed-by: NZhao Yakui <yakui.zhao@intel.com>
Acked-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

This corresponds to a fix to UMS back in 2007.  Fixes fd.o bug #20115.
Signed-off-by: NMa Ling <ling.ma@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

I had one report of flicker due to FIFO underruns on 845G.  Scott was
kind enough to test a few patches and report success with this one.
Looks like 845G measures FIFO size slightly differently than other
chips, and we were also clobbering the FIFO burst length.  Fixing both
of those issues gives him a healthy machine again.

Note that we still only adjust plane A's watermark in the 830/845
case.  If someone is willing to test we could support a bigger variety
of dual-head 830/845 configurations with a bit more code.

Fixes fdo bug #19304 (again).
Reported-by: NScott Hansen <scottandchrystie@comcast.net>
Tested-by: NScott Hansen <scottandchrystie@comcast.net>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

This adds embedded DisplayPort support on next mobile chip which
aims to replace origin LVDS port. VBT's driver feature block has
been used to determine the type of current internal panel for eDP
or LVDS.

Currently no panel fitting support for eDP and backlight control
would be added in future.
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

During pipe DPMS off, instead of busy waiting pipe off, insert
delays during wait and don't loop after enough tries which matches
spec requirement. Also try to match DPMS on path by disable FDI TX
PLL in DPMS off. Disable PF by writing PF_WIN_SZ which really trigger
the update.
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

This does VGA disable like DDX driver. SR01 bit 5 should be set
before VGA plane disable through control register, otherwise we
might get random crash and lockups.
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

If no planes are enabled, the self-refresh calculation may end up doing
a divide by zero.  This patch should prevent that by making sure at
least one of the CRTCs had a valid hdisplay value.
Reported-by: NEric Anholt <eric@anholt.net>
Tested-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

If you're pushing a plane hard (i.e. you need most or all of the FIFO
entries just to cover your frame refresh latency), the watermark level
may end up being negative.  So fix up the signed vs. unsigned math in
the calculation function to handle this correctly, giving all available
FIFO entries to such a configuration.
Reported-by: NEric Anholt <eric@anholt.net>
Tested-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

I discovered several bugs in the FIFO code that was recently applied.
Some of them fell into the "how did this ever work" category, since in
some cases we were using the wrong FIFO size values, and the
calculations ended up being way off.

This patch fixes all the bugs I found, and works well on my GM45, 915GM
and 855GM test machines; but as usual with these sorts of patches
broader testing is definitely requested (in particular this patch
affects 830, 845 and 865 for which I don't have test hardware).

Overall, the patch clarifies the watermark calculation function by
adding some comments and debug info, and making the variable names a
bit clearer.  The "get FIFO size" portion of the code has also been
corrected, so we should be able to properly detect the FIFO allocations
for each pipe, for use in the watermark calculation.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

The 915 and 945 scanout engines can handle frame buffers up to 4096 pixels
wide. Pre-9xx hardware has an 8192 byte stride limit, and so we leave the
existing 2048 max in place.

I'm not sure why we limit the height to the same value; there's no intrinsic
hardware limit in the scanout engine.
Signed-off-by: NKeith Packard <keithp@keithp.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Vbios will set lvds register correctly based on
current algorithm for lingle/dual Channel LVDS when
system boot, so we can accept this configuration
directly, regardless of LVDS enable status.

It fixed freedesktop.org bug #22262
Signed-off-by: NFlorian Mickler <florian@mickler.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

For some reason, the DP clocks were based off a 100MHz reference instead of
the standard 96MHz reference. This caused some DP monitors to fail to lock
to the signal.
Signed-off-by: NKeith Packard <keithp@keithp.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

We are seeing compilation failures on i386 in some environments due
to an undefined reference as below:

    ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!

This is generated due to a raw 64 bit divide in the i915 driver.  Fix up
this raw divide.
Signed-off-by: NAndy Whitcroft <apw@canonical.com>
Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

This patch from jbarnes and myself adds FIFO watermark control to the
driver.  This is needed for both power saving features on new platforms
with the so-called "big FIFO" and for controlling FIFO allocation
between pipes in multi-head configurations.

It's also necessary infrastructure to support things like framebuffer
compression and configuration supportability checks (i.e. checking a
configuration against available bandwidth).
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NShaohua Li <shaohua.li@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

The array of DAC limits was only ever referenced with #defined constant
offsets, and keeping those #define values in sync with the array itself was a
nuisance. This will make future changes to the set of DAC limits less
error-prone.
Signed-off-by: NKeith Packard <keithp@keithp.com>

Signed-off-by: NKeith Packard <keithp@keithp.com>