1. 22 5月, 2013 1 次提交
  2. 08 5月, 2013 1 次提交
    • S
      KVM/MIPS32: MMU/TLB operations for the Guest. · 858dd5d4
      Sanjay Lal 提交于
      - Note that this file is statically linked with the rest of the host kernel (KSEG0). This is because kernel modules are
      loaded into mapped space on MIPS and we want to make sure that we don't get any host kernel TLB faults while
      manipulating TLBs.
      - Virtual Guest TLBs are implemented as 64 entry array regardless of the number of host TLB entries.
      - Shadow TLBs map Guest virtual addresses to Host physical addresses.
      
          - TLB miss handling details:
              Guest KSEG0 TLBMISS (0x40000000 – 0x60000000): Transparent to the Guest.
              Guest KSEG2/3 (0x60000000 – 0x80000000) & Guest UM TLBMISS (0x00000000 – 0x40000000)
                  Lookup in Guest/Virtual TLB
                  If an entry doesn’t match
                      deliver appropriate TLBMISS LD/ST exception to the guest
                  If entry does exist in the Guest TLB and is NOT Valid
                      Deliver TLB invalid exception to the guest
                  If entry does exist in the Guest TLB and is VALID
                      Inject the TLB entry into the Shadow TLB
      Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
      Cc: kvm@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      858dd5d4