In some cases, like when you've got a "Microsoft Wireless Keyboard 2000"
connected to dwc2 with a hub, expected that we'll get some transfer
errors sometimes.  The controller is expected to try at least 3 times
before giving up.  See figure "Figure A-67. Normal HS CSPLIT 3 Strikes
Smash" in the USB spec.

The dwc2 controller has a way to support this by using the "EC_MC"
field.  The Raspberry Pi driver has logic for setting this right.  See
fiq_fsm_queue_split_transaction() in their "dwc_otg_hcd.c".  Let's use
the same logic.

After making this change, we no longer get dropped characters from the
above mentioned keyboard.  Other devices on the same bus as the keyboard
also behave more properly.

Thanks for Julius Werner for the expert analysis and suggestions.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Masks for HCDMA.CTD and HCDMA.DMAAddr are incorrect. As we always
start from first descriptor, no need to mask the address anyway.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Use Streaming DMA mappings to handle cache coherency of frame list and
descriptor list. Cache are always flushed before controller access it
or before cpu access it.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

As descriptor dma mode does not support split transfers, it can't be
enabled for high speed devices. Add a core parameter to enable it for
full speed devices.

Ensure frame list and descriptor list are correctly freed during
disconnect.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Fix a duplicate argument warning reported by 0-DAY kernel test
infrastructure in the following patch:
77dbf713 usb: dwc2: host: add disconnect interrupt to host only interrupts
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

If an interrupt rises during hibernation process, dwc2 will assert
interrupt line to interrupt controller. If interrupt is level
sensitive, interrupt handler will be called in a loop because dwc2
will not be able to clear it while controller is hibernated.
Thus, clear all controller interrupts before hibernation entry.
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

GINTSTS.DisconnInt is host only interrupt and should be disable after
dwc2_disable_host_interrupts is called.
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Frame number is reset in hardware after exiting hibernation.
Thus, reset frame_number and ensure qh are queued with correct
sched_frame.

Otherwise, qh->sched_frame may be too high compared to
current frame number (which is 0). This can delay addition of qh in
the list of transfers until frame number reaches qh->sched_frame.
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

When entering hibernation hprt0 must be read using dwc2_read_hprt0().
Otherwise, any set hprt0 status bits will be cleared when restoring
hprt0 on exit from hibernation.
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch switches calls to readl/writel to their
dwc2_readl/dwc2_writel equivalents which preserve platform endianness.

This patch is necessary to access dwc2 registers correctly on big-endian
systems such as the mips based SoCs made by Lantiq. Then dwc2 can be
used to replace ifx-hcd driver for Lantiq platforms found e.g. in
OpenWrt.

The patch was autogenerated with the following commands:
$EDITOR core.h
sed -i "s/\<readl\>/dwc2_readl/g" *.c hcd.h hw.h
sed -i "s/\<writel\>/dwc2_writel/g" *.c hcd.h hw.h

Some files were then hand-edited to fix checkpatch.pl warnings about
too long lines.
Signed-off-by: NAntti Seppälä <a.seppala@gmail.com>
Signed-off-by: NVincent Pelletier <plr.vincent@gmail.com>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch fix spelling typo inv various part of sources.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Acked-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NJiri Kosina <jkosina@suse.com>

Register backup function can be called from atomic context. Instead
of using atomic memory pool, embed backup storage space in
struct dwc2_hsotg.

Also add a valid flag in each struct as NULL pointer can't be used as
the content validity check any more.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

dwc2 may not be able to exit from hibernation if the hardware
does not provide a way to detect resume signalling in this state.
Thus, add the possibility to disable hibernation feature.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

As dwc2 pci module is now exporting dwc2 platform device, include
platform.o in dwc2-y and remove USB_DWC2_PLATFORM configuration
option. Driver will be built as two modules, dwc2.ko and dwc2_pci.ko.
dwc2.ko is the new platform driver.

Remove all EXPORT_SYMBOL_GPL as they are not needed any more.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

So the parameters can be used in both host and gadget modes.
Also consolidate param functions in the core.h
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This is required due to an Intel specific hardware issue. Where id-
pin setup causes glitches on the interrupt line when CONIDSTSCHG
interrupt is enabled.

Specify external_id_pin_ctl when an external driver (for example phy)
can handle id change, so that CONIDSTSCHG interrupt can be disabled
from the controller.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

When suspending usb bus, phy driver may disable controller power.
In this case, registers need to be saved on suspend and restored
on resume.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Fixed 3 typos in comments
Signed-off-by: NMickael Maison <mickael.maison@gmail.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Make dwc2_handle_common_intr call the gadget interrupt function when operating
in peripheral mode. Remove the spinlock functions in s3c_hsotg_irq as
dwc2_handle_common_intr() already has the spinlocks.

Move the registeration of the IRQ to common code for platform and PCI.

Remove duplicate interrupt conditions that was in gadget, as those are handled
by dwc2 common interrupt handler.
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Clip max_transfer_size to 65535 for host. dwc2_hc_setup_align_buf()
allocates coherent buffers with this size, and if it's too large we
can exhaust the coherent DMA pool.

Tested on Raspberry Pi and Altera SOCFPGA.
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

According to the "dr_mode", the otg controller can work as
device role and host role. Some boards always want to use host mode
and some other boards want to use gadget mode. We use the dts setting
to set dwc2's mode, rather than fixing it to whatever hardware says.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The documentation for GNPTXFSIZ says that "For host mode, this field
is always valid."  Since we're already switching to host mode for
HPTXFSIZ, let's also read GNPTXFSIZ in host mode.

On an rk3288 SoC, without this change we see this at bootup:
  dwc2 ff580000.usb: gnptxfsiz=00100400
  dwc2 ff580000.usb: 128 invalid for host_nperio_tx_fifo_size. Check HW configuration.

After this change we see:
  dwc2 ff580000.usb: gnptxfsiz=04000400
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064
32-bit words. But the GRXFSIZ, GNPTXFSIZ, and HPTXFSIZ register defaults
to 0x2000 or 8192 32-bit words. So the driver cannot just use the fifo sizes
as read from those registers.

For platforms that face the same issue, this commits sets the RX, periodic TX,
and non-periodic TX fifo size to those that are recommended v2.93a spec for
the DWC2 IP. Implements Method #2 from the Synopsys v2.93a spec for the DWC2.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Reviewed-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Commit beb7e592 "staging: dwc2: add check on dwc2_core_reset
return" broke the B -> A role switching on OTG-enabled platforms.
This commit fixes it.
Reported-by: NDinh Nguyen <dinguyen@altera.com>
Tested-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The DWC2 driver should now be in good enough shape to move out of
staging. I have stress tested it overnight on RPI running mass
storage and Ethernet transfers in parallel, and for several days
on our proprietary PCI-based platform.
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Fixes the following sparse warning:

drivers/staging/dwc2/core.c:2672:6: warning:
 symbol 'dwc2_set_param_uframe_sched' was not declared. Should it be static?
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The function dwc2_get_hwparams() was in an awkward place, mixed
in with the dwc2_set_param* functions. Move it down after those
functions.
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Remove stale comment after changing dwc2_set_parameters() to void
function
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Rename dwc2_check_core_status() to dwc2_is_controller_alive(), and
make it a boolean function. Also change the message when the
controller is dead to say "dead" instead of "disconnected".
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Remove useless cast in dwc2_get_otg_version()
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

NO_FS_PHY_HW_CHECKS is never defined, so remove the conditional
code that checks for it being set
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

We were not checking the return value from any of these functions,
so make them void functions
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

DWC2_PARAM_TEST is not a very good name for this macro, so rename
it to DWC2_OUT_OF_BOUNDS
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

If the GRSTCTL_CSFTRST self-clearing bit never comes
back to 0 for any reason, the controller is under reset
state and cannot be used. It's preferable to abort
initialization in such case.
Signed-off-by: NJulien Delacou <julien.delacou@st.com>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Pending interrupts clearing is done in dwc2_enable_common_interrupts
so we don't need to do it twice.
Signed-off-by: NJulien Delacou <julien.delacou@st.com>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Fixed coding style issue where lines are indented with spaces
instead of tabs.
Signed-off-by: NLuis Ortega Perez de Villar <luiorpe1@upv.es>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The transfer scheduler in the dwc2 driver is pretty basic, not to
mention buggy. It works fairly well with just a couple of devices
plugged in, but if you add, say, multiple devices with periodic
endpoints, the scheduler breaks down and can't even enumerate all
the devices.

To improve this, import the "microframe scheduler" patch from the
driver in the downstream Raspberry Pi kernel, which is based on
the Synopsys vendor driver. The original patch came from Denx
(http://git.denx.de/?p=linux-denx.git) and was commited to the
raspberrypi.org git tree by "popcornmix" (Dom Cobley).

I have added a driver parameter for this, enabled by default, in
case anyone has problems with it and needs to disable it. I don't
think we should add a DT binding for that, though, since I plan
to remove the option once any bugs are fixed.

[raspberrypi.org patch from Dom Cobley]
Signed-off-by: NDom Cobley <popcornmix@gmail.com>
[adapted to dwc2 driver by Paul Zimmerman]
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Correct spelling typo in comments
Singend-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The HWCFG4 register stores the supported utmi width values (8, 16 or
both). This commit reads that value and validates the configured value
against that.

If no (valid) value is given, the parameter defaulted to 8 bits
previously.  However, the documentation for dwc2_core_params_struct
suggests that the default should have been 16. Also, the pci bindings
explicitely set the value to 16, so this commit changes the default to
16 bits (if supported, 8 bits otherwise).

With the default changed, the value set in pci.c is changed to -1 to
make it autodetected as well.
Signed-off-by: NMatthijs Kooijman <matthijs@stdin.nl>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Before, the hwcfg registers were read at device init time, but
interpreted at various parts in the code. This commit unpacks the hwcfg
register values into a struct with properly labeled variables at init
time, which makes all the other code using these values more consise and
easier to read. Some values that were previously stored in the hsotg
struct are now moved into this new struct as well.

In addition to the hwcfg registers, the contents of some fifo size
registers are also unpacked. The hwcfg registers are read-only, so they
can be safely stored. The fifo size registers are read-write registers,
but their power-on values are significant: they give the maximum depth
of the fifo they describe.

This commit mostly moves code, but also attempts to simplify some
expressions from (val >> shift) & (mask >> shift) to
(val & mask) >> shift.

Finally, all of the parameters read from the hardware are debug printed
after unpacking them, so a bunch of debug prints can be removed from
other places.
Signed-off-by: NMatthijs Kooijman <matthijs@stdin.nl>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>