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  1. 19 6月, 2006 2 次提交
  3. 18 6月, 2006 3 次提交
  5. 05 6月, 2006 1 次提交
  7. 17 5月, 2006 1 次提交
    • D
      [ARM] 3529/1: s3c24xx: fix restoring control register with undefined instruction · c3fb0416
      由 Dimitry Andric 提交于 
      Patch from Dimitry Andric

In arch/arm/mach-s3c2410/sleep.S, the coprocessor registers are saved at
suspend time, and restored at resume time. However, an undefined
instruction is used when attempting to restore a non-existent "auxiliary
control register".  This leads to a crash on S3C2412, which has an ARM926
core instead of an ARM920.

At suspend time, the following fragment runs:

	mrc	p15, 0, r7, c2, c0, 0	@ translation table base address
	mrc	p15, 0, r8, c2, c0, 0	@ auxiliary control register
	mrc	p15, 0, r9, c1, c0, 0	@ control register

and at resume time, the following fragment runs:

	mcr	p15, 0, r7, c2, c0, 0		@ translation table base
	mcr	p15, 0, r8, c1, c1, 0		@ auxilliary control
	...
	mcr	p15, 0, r9, c1, c0, 0		@ turn on MMU, etc

There are several problems with these fragments:
1. The ARM920 and ARM926 cores don't have any "auxiliary control
   register", at least not according to the ARM920 and ARM926 TRM's.
2. The 2nd line of suspend erroneously saves the c2 register again.
3. This saved c2 value is restored using an undefined instruction.  For
   some reason this does not crash on ARM920, but does crash on ARM926.

The following patch fixes all these problems.
Signed-off-by: NDimitry Andric <dimitry@andric.com>
Yes, this looks sensible
Signed-off-by: NBen Dooks <ben-linux@fluff.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      c3fb0416
  9. 13 4月, 2006 1 次提交
  11. 12 4月, 2006 1 次提交
  13. 10 4月, 2006 2 次提交
  15. 02 4月, 2006 6 次提交
  17. 24 3月, 2006 1 次提交
  19. 22 3月, 2006 9 次提交
  21. 16 3月, 2006 1 次提交
  23. 11 2月, 2006 1 次提交
  25. 10 2月, 2006 1 次提交
  27. 09 2月, 2006 2 次提交
  29. 02 2月, 2006 2 次提交
  31. 26 1月, 2006 1 次提交
  33. 14 1月, 2006 1 次提交
  35. 13 1月, 2006 1 次提交
  37. 10 1月, 2006 1 次提交
  39. 09 1月, 2006 1 次提交
    • R
      [PATCH] IRQ type flags · 9ded96f2
      由 Russell King 提交于 
      Some ARM platforms have the ability to program the interrupt controller to
detect various interrupt edges and/or levels.  For some platforms, this is
critical to setup correctly, particularly those which the setting is dependent
on the device.

Currently, ARM drivers do (eg) the following:

	err = request_irq(irq, ...);

	set_irq_type(irq, IRQT_RISING);

However, if the interrupt has previously been programmed to be level sensitive
(for whatever reason) then this will cause an interrupt storm.

Hence, if we combine set_irq_type() with request_irq(), we can then safely set
the type prior to unmasking the interrupt.  The unfortunate problem is that in
order to support this, these flags need to be visible outside of the ARM
architecture - drivers such as smc91x need these flags and they're
cross-architecture.

Finally, the SA_TRIGGER_* flag passed to request_irq() should reflect the
property that the device would like.  The IRQ controller code should do its
best to select the most appropriate supported mode.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      9ded96f2
  41. 08 1月, 2006 1 次提交