1. 11 3月, 2011 5 次提交
    • C
      drivers/edac: provide support for tile architecture · 5c770755
      Chris Metcalf 提交于
      Add tile support for the EDAC driver, which provides unified system
      error (memory, PCI, etc.) reporting. For now, the TILEPro port
      reports memory correctable error (CE) only.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      5c770755
    • C
      tile on-chip network driver: sync up with latest fixes · d91c6412
      Chris Metcalf 提交于
      Combine the "command" and "completion" locks into a single lock,
      on each egress queue, to improve efficiency.
      
      Support the use of 4KB pages in the "egress queue".
      
      Delete the unused "duplicate ACK compression" code.
      
      Filter "bad" (i.e. truncated) packets.
      
      Avoid corrupting "dev->napi_list", by sequentializing modifications.
      
      Deregister for incoming packets during stop, to reduce unexpected
      interrupts.  Also, encourage active NAPI loops to complete before
      we disable NAPI, which would otherwise crash.
      
      Free any pending completions after shutting down LEPP.
      
      Use a single, permanently registered, IRQ handler, to avoid situations
      in which the IRQ handler was firing after being freed, and ignore any
      "unexpected" interrupts.
      
      Drop egress packets, instead of spinning, if the hardware cannot keep
      up, or is disconnected.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      d91c6412
    • C
      arch/tile: support 4KB page size as well as 64KB · 76c567fb
      Chris Metcalf 提交于
      The Tilera architecture traditionally supports 64KB page sizes
      to improve TLB utilization and improve performance when the
      hardware is being used primarily to run a single application.
      
      For more generic server scenarios, it can be beneficial to run
      with 4KB page sizes, so this commit allows that to be specified
      (by modifying the arch/tile/include/hv/pagesize.h header).
      
      As part of this change, we also re-worked the PTE management
      slightly so that PTE writes all go through a __set_pte() function
      where we can do some additional validation.  The set_pte_order()
      function was eliminated since the "order" argument wasn't being used.
      
      One bug uncovered was in the PCI DMA code, which wasn't properly
      flushing the specified range.  This was benign with 64KB pages,
      but with 4KB pages we were getting some larger flushes wrong.
      
      The per-cpu memory reservation code also needed updating to
      conform with the newer percpu stuff; before it always chose 64KB,
      and that was always correct, but with 4KB granularity we now have
      to pay closer attention and reserve the amount of memory that will
      be requested when the percpu code starts allocating.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      76c567fb
    • C
      arch/tile: add some more VMSPLIT options and use consistent naming · 09c17eab
      Chris Metcalf 提交于
      This renames 3G_OPT to 2_75G, and adds 2_5G and 2_25G.
      
      For memory-intensive applications that are also network-buffer
      intensive it can be helpful to be able to tune the virtual address
      of the start of kernel memory.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      09c17eab
    • C
      arch/tile: fix some comments and whitespace · 5fb682b0
      Chris Metcalf 提交于
      This is a grab bag of changes with no actual change to generated code.
      This includes whitespace and comment typos, plus a couple of stale
      comments being removed.
      Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
      5fb682b0
  2. 02 3月, 2011 14 次提交
  3. 25 2月, 2011 1 次提交
  4. 24 2月, 2011 5 次提交
  5. 22 2月, 2011 15 次提交