- 11 2月, 2016 1 次提交
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由 Chris Brandt 提交于
When building an XIP kernel, the linker script needs to be much different than a conventional kernel's script. Over time, it's been difficult to maintain both XIP and non-XIP layouts in one linker script. Therefore, this patch separates the two procedures into two completely different files. The new linker script is essentially a straight copy of the current script with all the non-CONFIG_XIP_KERNEL portions removed. Additionally, all CONFIG_XIP_KERNEL portions have been removed from the existing linker script...never to return again. It should be noted that this does not fix any current XIP issues, but rather is the first move in fixing them properly with subsequent patches. Signed-off-by: NChris Brandt <chris.brandt@renesas.com> Acked-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 08 2月, 2016 3 次提交
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由 Kees Cook 提交于
The use of CONFIG_DEBUG_RODATA is generally seen as an essential part of kernel self-protection: http://www.openwall.com/lists/kernel-hardening/2015/11/30/13 Additionally, its name has grown to mean things beyond just rodata. To get ARM closer to this, we ought to rearrange the names of the configs that control how the kernel protects its memory. What was called CONFIG_ARM_KERNMEM_PERMS is realy doing the work that other architectures call CONFIG_DEBUG_RODATA. This redefines CONFIG_DEBUG_RODATA to actually do the bulk of the ROing (and NXing). In the place of the old CONFIG_DEBUG_RODATA, use CONFIG_DEBUG_ALIGN_RODATA, since that's what the option does: adds section alignment for making rodata explicitly NX, as arm does not split the page tables like arm64 does without _ALIGN_RODATA. Also adds human readable names to the sections so I could more easily debug my typos, and makes CONFIG_DEBUG_RODATA default "y" for CPU_V7. Results in /sys/kernel/debug/kernel_page_tables for each config state: # CONFIG_DEBUG_RODATA is not set # CONFIG_DEBUG_ALIGN_RODATA is not set ---[ Kernel Mapping ]--- 0x80000000-0x80900000 9M RW x SHD 0x80900000-0xa0000000 503M RW NX SHD CONFIG_DEBUG_RODATA=y CONFIG_DEBUG_ALIGN_RODATA=y ---[ Kernel Mapping ]--- 0x80000000-0x80100000 1M RW NX SHD 0x80100000-0x80700000 6M ro x SHD 0x80700000-0x80a00000 3M ro NX SHD 0x80a00000-0xa0000000 502M RW NX SHD CONFIG_DEBUG_RODATA=y # CONFIG_DEBUG_ALIGN_RODATA is not set ---[ Kernel Mapping ]--- 0x80000000-0x80100000 1M RW NX SHD 0x80100000-0x80a00000 9M ro x SHD 0x80a00000-0xa0000000 502M RW NX SHD Signed-off-by: NKees Cook <keescook@chromium.org> Reviewed-by: NLaura Abbott <labbott@fedoraproject.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Code run via soft_restart() is run with the MMU disabled, so we need to pass the identity map physical address rather than the address obtained from virt_to_phys(). Therefore, replace virt_to_phys() with virt_to_idmap() for all callers of soft_restart(). Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk> -
由 Russell King 提交于
Make virt_to_idmap() return an unsigned long rather than phys_addr_t. Returning phys_addr_t here makes no sense, because the definition of virt_to_idmap() is that it shall return a physical address which maps identically with the virtual address. Since virtual addresses are limited to 32-bit, identity mapped physical addresses are as well. Almost all users already had an implicit narrowing cast to unsigned long so let's make this official and part of this interface. Tested-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 27 1月, 2016 2 次提交
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由 Andiii 提交于
arm: irq: l2c: do not print error in case of missing l2c from dtb In some architectures the L2 cache controller is integrated in the processor's block itself and it doesn't use any external cache controller. This means that an entry in the board's dtb related to the l2c is not necessary. Distinguish between error codes and do not print anything in case l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV. This patch mutes the following error message: L2C: failed to init: -19 on boards like odroid-xu4, cortex A7/A15, which don't have external cache controller. Signed-off-by: NAndi Shyti <andi.shyti@samsung.com> Reported-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Juri Lelli 提交于
Instead of looping through all cpus calling set_capacity_scale, we can initialise cpu_scale per-cpu variables to SCHED_CAPACITY_SCALE with their definition. Acked-by: NVincent Guittot <vincent.guittot@linaro.org> Signed-off-by: NJuri Lelli <juri.lelli@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 05 1月, 2016 2 次提交
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由 Jens Wiklander 提交于
Switch to use a generic interface for issuing SMC/HVC based on ARM SMC Calling Convention. Removes now the now unused psci-call.S. Acked-by: NWill Deacon <will.deacon@arm.com> Reviewed-by: NMark Rutland <mark.rutland@arm.com> Tested-by: NMark Rutland <mark.rutland@arm.com> Acked-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NJens Wiklander <jens.wiklander@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jens Wiklander 提交于
Adds implementation for arm-smccc and enables CONFIG_HAVE_SMCCC for architectures that may support arm-smccc. It's the responsibility of the caller to know if the SMC instruction is supported by the platform. Reviewed-by: NLars Persson <lars.persson@axis.com> Signed-off-by: NJens Wiklander <jens.wiklander@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 04 1月, 2016 2 次提交
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由 Ivaylo Dimitrov 提交于
So it can be used by code outside arch/arm/kernel/. Fix save_atags() declaration to match its definition while at it. Signed-off-by: NIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Ard Biesheuvel 提交于
The PJ4 inline asm sequence to write to cp15 cannot be built in Thumb-2 mode, due to the way it performs arithmetic on the program counter, so it is built in ARM mode instead. However, building C files in ARM mode under CONFIG_THUMB2_KERNEL is problematic, since the instrumentation performed by subsystems like ftrace does not expect having to deal with interworking branches. Since the sequence in question is simply a poor man's ISB instruction, let's use a straight 'isb' instead when building in Thumb2 mode. Thumb2 implies V7, so 'isb' should always be supported in that case. Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 30 12月, 2015 1 次提交
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由 Al Viro 提交于
Cc: stable@vger.kernel.org # 3.15+ Reviewed-by: NJeff Layton <jeff.layton@primarydata.com> Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
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- 22 12月, 2015 4 次提交
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由 Will Deacon 提交于
It's all very well providing an events directory to userspace that details our events in terms of "event=0xNN", but if we don't define how to encode the "event" field in the perf attr.config, then it's a waste of time. This patch adds a single format entry to describe that the event field occupies the bottom 8 bits of our config field on ARMv7. Signed-off-by: NWill Deacon <will.deacon@arm.com> -
由 Marc Zyngier 提交于
Having IPI_CPU_BACKTRACE as SGI15 may not work if the kernel is running in non-secure mode and that the secure firmware has decided to follow ARM's recommendations that SGI8-15 should be reserved for secure purpose. Now that we are "only" using SGI0-6, change IPI_CPU_BACKTRACE to use SGI7, which makes it more likely to work. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Marc Zyngier 提交于
Since 9a46ad6d ("smp: make smp_call_function_many() use logic similar to smp_call_function_single()"), the core IPI handling has been simplified, and generic_smp_call_function_interrupt is now the same as generic_smp_call_function_single_interrupt. This means that one of IPI_CALL_FUNC and IPI_CALL_FUNC_SINGLE has become redundant. We can then safely drop IPI_CALL_FUNC_SINGLE, and use only IPI_CALL_FUNC. This has the advantage of reducing the number of SGI IDs we're using (a fairly scarse resource). Tested on a dual A7 board. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Lorenzo Pieralisi 提交于
The suspend() hook in the cpuidle_ops struct is always called on the cpu entering idle, which means that the cpu parameter passed to the suspend hook always corresponds to the local cpu, making it somewhat redundant. This patch removes the logical cpu parameter from the ARM cpuidle_ops.suspend hook and updates all the existing kernel implementations to reflect this change. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: NLina Iyer <lina.iyer@linaro.org> Tested-by: NLina Iyer <lina.iyer@linaro.org> Tested-by: Jisheng Zhang <jszhang@marvell.com> [psci] Cc: Lina Iyer <lina.iyer@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 21 12月, 2015 1 次提交
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由 Stefano Stabellini 提交于
Introduce CONFIG_PARAVIRT and PARAVIRT_TIME_ACCOUNTING on ARM. The only paravirt interface supported is pv_time_ops.steal_clock, so no runtime pvops patching needed. This allows us to make use of steal_account_process_tick for stolen ticks accounting. Signed-off-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: NChristopher Covington <cov@codeaurora.org> Acked-by: NIan Campbell <ian.campbell@citrix.com> Acked-by: NRussell King <linux@arm.linux.org.uk>
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- 18 12月, 2015 1 次提交
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由 Arnd Bergmann 提交于
Moving ARCH_VERSATILE into ARCH_MULTIPLATFORM means that it no longer works as the default target for MMU-less kernels. While we might want to get that working again in the future, it's also a rather bad default, and it makes sense to make ARM_SINGLE_V7M the default because that is what realistically all NOMMU users on ARM are using, and it actually is what gets selected by default in the absence of versatile in the choice statement. Related to this, 'allnoconfig' kernels fail to link with the new default, as they do not include a machine record: arm-linux-gnueabi-ld: no machine record defined For ARCH_MULTIPLATFORM kernels, we avoid this error by using a default machine descriptor that works for all trivial platforms, like ARCH_VIRT. The same reasoning applies for ARM_SINGLE_V7M, as that can also boot with empty machine descriptors both on qemu and on real hardware, as long as all the drivers are present. We could also follow up with a patch to remove the existing machine descriptors for the ARMv7M platforms, the only callback pointer the four platforms contain today is the armv7m_restart handler and we can simply make that the default for v7M with an add-on patch. Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 17 12月, 2015 2 次提交
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由 Nicolas Pitre 提交于
The ARM compiler inserts calls to __aeabi_idiv() and __aeabi_uidiv() when it needs to perform division on signed and unsigned integers. If a processor has support for the sdiv and udiv instructions, the kernel may overwrite the beginning of those functions with those instructions and a "bx lr" to get better performance. To ensure that those functions are aligned to a 32-bit word for easier patching (which might not always be the case in Thumb mode) and that the two patched instructions end up in the same cache line, a 8-byte alignment is enforced when ARM_PATCH_IDIV is selected. This was heavily inspired by a previous patch from Stephen Boyd. Signed-off-by: NNicolas Pitre <nico@linaro.org> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Prasanna Karthik 提交于
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Signed-off-by: NPrasanna Karthik <mkarthi3@visteon.com> Signed-off-by: NNathan Lynch <nathan_lynch@mentor.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 15 12月, 2015 1 次提交
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由 Shengjiu Wang 提交于
__user_swpX_asm maybe failed in first STREX operation, emulate_swpX will try again, but the *data has been changed in first time. which causes the result is wrong. This patch is to fix this issue. When STREX succeed, change the *data. if it fail, *data is not changed. Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 14 12月, 2015 2 次提交
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由 Ard Biesheuvel 提交于
This adds support to the kernel proper for booting via UEFI. It shares most of the code with arm64, so this patch mostly just wires it up for use with ARM. Note that this does not include the EFI stub, it is added in a subsequent patch. Tested-by: NRyan Harkin <ryan.harkin@linaro.org> Reviewed-by: NMatt Fleming <matt@codeblueprint.co.uk> Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
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由 Ard Biesheuvel 提交于
This enables the generic early_ioremap implementation for ARM. It uses the fixmap region reserved for kmap. Since early_ioremap is only supported before paging_init(), and kmap is only supported afterwards, this is guaranteed not to cause any clashes. Tested-by: NRyan Harkin <ryan.harkin@linaro.org> Reviewed-by: NMatt Fleming <matt@codeblueprint.co.uk> Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
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- 05 12月, 2015 2 次提交
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由 Rusty Russell 提交于
Makes it easier to handle init vs core cleanly, though the change is fairly invasive across random architectures. It simplifies the rbtree code immediately, however, while keeping the core data together in the same cachline (now iff the rbtree code is enabled). Acked-by: NPeter Zijlstra <peterz@infradead.org> Reviewed-by: NJosh Poimboeuf <jpoimboe@redhat.com> Signed-off-by: NRusty Russell <rusty@rustcorp.com.au> Signed-off-by: NJiri Kosina <jkosina@suse.cz>
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由 Russell King 提交于
When printing the DACR value, we print the domain register value. This is incorrect, as with SW_PAN enabled, that is the current setting, rather than the faulting context's setting. Arrange to print the faulting domain's saved DACR value instead. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 02 12月, 2015 2 次提交
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由 Masahiro Yamada 提交于
These smp_operations structures are not over-written, so add "const" qualifier and replace __initdata with __initconst. Also, add "static" where it is possible. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NMoritz Fischer <moritz.fischer@ettus.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> # qcom part Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NPatrice Chotard <patrice.chotard@st.com> Acked-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NWei Xu <xuwei5@hisilicon.com> Acked-by: NFlorian Fainelli <f.fainelli@gmail.com> Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: NShawn Guo <shawnguo@kernel.org> Acked-by: NMatthias Brugger <matthias.bgg@gmail.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NNicolas Pitre <nico@linaro.org> Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Arnd Bergmann 提交于
In a multiplatform configuration, we may end up building a kernel for both Marvell PJ1 and an ARMv4 CPU implementation. In that case, the xscale-cp0 code is built with gcc -march=armv4{,t}, which results in a build error from the coprocessor instructions. Since we know this code will only have to run on an actual xscale processor, we can simply build the entire file for ARMv5TE. Related to this, we need to handle the iWMMXT initialization sequence differently during boot, to ensure we don't try to touch xscale specific registers on other CPUs from the xscale_cp0_init initcall. cpu_is_xscale() used to be hardcoded to '1' in any configuration that enables any XScale-compatible core, but this breaks once we can have a combined kernel with MMP1 and something else. In this patch, I replace the existing cpu_is_xscale() macro with a new cpu_is_xscale_family() macro that evaluates true for xscale, xsc3 and mohawk, which makes the behavior more deterministic. The two existing users of cpu_is_xscale() are modified accordingly, but slightly change behavior for kernels that enable CPU_MOHAWK without also enabling CPU_XSCALE or CPU_XSC3. Previously, these would leave leave PMD_BIT4 in the page tables untouched, now they clear it as we've always done for kernels that enable both MOHAWK and the support for the older CPU types. Since the previous behavior was inconsistent, I assume it was unintentional. Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 26 11月, 2015 1 次提交
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由 Gabriele Paoloni 提交于
Commit b3a72384 ("ARM/PCI: Replace pci_sys_data->align_resource with global function pointer") introduced an ARM-specific align_resource() function pointer. This is not portable to other arches and doesn't work for platforms with two different PCIe host bridge controllers. Move the function pointer to the pci_host_bridge structure so each host bridge driver can specify its own align_resource() function. Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de>
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- 18 11月, 2015 1 次提交
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由 Russell King 提交于
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 17 11月, 2015 1 次提交
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由 Ezequiel Garcia 提交于
The PendSV handler calls v7m_exception_entry which disables IRQs. Therefore, since IRQs are already disabled, the PendSV handler can return using ret_to_user_from_irq. Signed-off-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 16 11月, 2015 2 次提交
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由 Drew Richardson 提交于
Add additional information about the ARM architected hardware events to make counters self describing. This makes the hardware PMUs easier to use as perf list contains possible events instead of users having to refer to documentation like the ARM TRMs. Signed-off-by: NDrew Richardson <drew.richardson@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Drew Richardson 提交于
The enums are not necessary and this allows the event values to be used to construct static strings at compile time. Signed-off-by: NDrew Richardson <drew.richardson@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 03 11月, 2015 1 次提交
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由 Gabriele Paoloni 提交于
dw_pcie_host_init() creates the PCI host bridge with pci_common_init_dev(), an ARM-specific function that supplies the ARM-specific pci_sys_data structure as the PCI "sysdata". To use dw_pcie_host_init() on other architectures, we will copy the internals of pci_common_init_dev() into pcie-designware.c instead of calling it, and dw_pcie_host_init() will supply the DesignWare pcie_port structure as "sysdata". Most ARM "sysdata" users are specific to non-DesignWare host bridges; they'll be unaffected because those bridges will continue to have the ARM pci_sys_data. Most of the rest are ARM-generic functions called by pci_common_init_dev(); these will be unaffected because dw_pcie_host_init() will no longer call pci_common_init(). But the ARM pcibios_align_resource() can be called by the PCI core for any bridge, so it can't depend on sysdata since it may be either pci_sys_data or pcie_port. Remove the pcibios_align_resource() dependency on sysdata by replacing the pci_sys_data->align_resource pointer with a global function pointer. This is less general (we can no longer have per-host bridge align_resource() methods), but the pci_sys_data->align_resource pointer was used only by Marvell (see mvebu_pcie_enable()), so this would only be a problem if we had a system with a combination of Marvell and other host bridges [bhelgaas: changelog] Signed-off-by: NGabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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- 27 10月, 2015 1 次提交
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由 Masahiro Yamada 提交于
This commit adds support for UniPhier outer cache controller. All the UniPhier SoCs are equipped with the L2 cache, while the L3 cache is currently only integrated on PH1-Pro5 SoC. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 26 10月, 2015 1 次提交
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由 Julia Lawall 提交于
for_each_child_of_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. The of_node_put is duplicated in front of each error return, because the function contains a later error return that is beyond the end of the for_each_child_of_node and thus doesn't need of_node_put. The semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression root,e; local idexpression child; iterator name for_each_child_of_node; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } @@ expression root,e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child + of_node_put(child); ? break; ... } ... when != child // </smpl> Additionally, concatenated a string in an affected line to avoid introducing a checkpatch warning. Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 23 10月, 2015 1 次提交
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由 Stephen Boyd 提交于
Now that __cpuinit has been removed, the __ref markings on these functions are useless. Remove them. This also reduces the size of the multi_v7_defconfig image: $ size before after text data bss dec hex filename 12683578 1470996 348904 14503478 dd4e36 before 12683274 1470996 348904 14503174 dd4d06 after presumably because now we don't have to jump to code in the .ref.text section and/or the noinline marking is removed. Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: <linux-omap@vger.kernel.org> Cc: <linux-arm-msm@vger.kernel.org> Cc: <spear-devel@list.st.com> Cc: <linux-tegra@vger.kernel.org> Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NBarry Song <baohua@kernel.org> Acked-by: NAndy Gross <agross@codeaurora.org> Acked-by: NViresh Kumar <vireshk@kernel.org> Acked-by: NThierry Reding <thierry.reding@gmail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NSudeep Holla <sudeep.holla@arm.com> Acked-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 09 10月, 2015 2 次提交
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由 Russell King 提交于
Rename feat_c3stop to twd_features to match the other variables in this file. Initialise it with the standard features that we always support, and arrange to set the CLOCK_EVT_FEAT_C3STOP when appropriate. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk> -
由 Marc Gonzalez 提交于
In 5388a6b2 ("ARM: SMP: Always enable clock event broadcast support") Russell noted that "the TWD local timers are unable to wake up the CPU when it is placed into a low power mode". However, some platforms do not stop the TWD block in low-power mode, and can thus use the TWD timer in one-shot mode, without setting up a broadcast device. Make the driver check for the "always-on" boolean property, and set the CLOCK_EVT_FEAT_C3STOP flag accordingly. Acked-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 03 10月, 2015 3 次提交
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由 Daniel Thompson 提交于
Currently on ARM when <SysRq-L> is triggered from an interrupt handler (e.g. a SysRq issued using UART or kbd) the main CPU will wedge for ten seconds with interrupts masked before issuing a backtrace for every CPU except itself. The new backtrace code introduced by commit 96f0e003 ("ARM: add basic support for on-demand backtrace of other CPUs") does not work correctly when run from an interrupt handler because IPI_CPU_BACKTRACE is used to generate the backtrace on all CPUs but cannot preempt the current calling context. This can be fixed by detecting that the calling context cannot be preempted and issuing the backtrace directly in this case. Issuing directly leaves us without any pt_regs to pass to nmi_cpu_backtrace() so we also modify the generic code to call dump_stack() when its argument is NULL. Acked-by: NHillf Danton <hillf.zj@alibaba-inc.com> Acked-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Doug Anderson 提交于
Dumping registers from other sleeping tasks in KGDB was totally failing for me. All registers were reported as 0 in many cases. The code was using task_pt_regs(task) to try to get other thread registers. This doesn't appear to be the right place to look. From my tests, I saw non-zero values in this structure when we were looking at a kernel thread that had a userspace task associated with it, but it contained the register values from the userspace task. So even in the cases where registers weren't reported as 0 we were still not showing the right thing. Instead of using task_pt_regs(task) let's use task_thread_info(task). This is the same place that is referred to when doing a dump of all sleeping task stacks (kdb_show_stack() -> show_stack() -> dump_backtrace() -> unwind_backtrace() -> thread_saved_sp()). As further evidence that this is the right thing to do, you can find the following comment in "gdbstub.c" right before it calls sleeping_thread_to_gdb_regs(): Pull stuff saved during switch_to; nothing else is accessible (or even particularly relevant). This should be enough for a stack trace. ...and if you look at switch_to() it only saves r4-r11, sp and lr. Those are the same registers that I'm getting out of the task_thread_info(). With this change you can use "info thread" to see all tasks in the kernel and you can switch to other tasks and examine them in gdb. Signed-off-by: NDoug Anderson <dianders@chromium.org> Tested-by: NStephen Boyd <sboyd@codeurora.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Mark Brand reports that a NEEDS_SYSCALL_FOR_CMPXCHG enabled kernel would open a security hole in the ghost syscall used to implement cmpxchg, as it fails to validate the user pointer. However, in order for this option to be enabled, you'd need to be building a pre-ARMv6 kernel with SMP support. There is only one system known which fits that, which is an early ARM SMP FPGA implementation based on the ARM926T. In any case, the Kconfig does not allow SMP to be enabled for pre-ARMv6 systems. Moreover, even if NEEDS_SYSCALL_FOR_CMPXCHG were to be enabled, the kernel would not build as __ARM_NR_cmpxchg64 is not defined. The simple answer is to remove the buggy code. Reported-by: NMark Brand <markbrand@google.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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