1. 05 6月, 2008 2 次提交
  2. 03 6月, 2008 1 次提交
  3. 31 5月, 2008 3 次提交
  4. 30 5月, 2008 8 次提交
  5. 29 5月, 2008 3 次提交
    • I
      sched: re-tune NUMA topologies · ea3f01f8
      Ingo Molnar 提交于
      improve the sysbench ramp-up phase and its peak throughput on
      a 16way NUMA box, by turning on WAKE_AFFINE:
      
                   tip/sched   tip/sched+wake-affine
      -------------------------------------------------
          1:             700              830    +15.65%
          2:            1465             1391    -5.28%
          4:            3017             3105    +2.81%
          8:            5100             6021    +15.30%
         16:           10725            10745    +0.19%
         32:           10135            10150    +0.16%
         64:            9338             9240    -1.06%
        128:            8599             8252    -4.21%
        256:            8475             8144    -4.07%
      -------------------------------------------------
        SUM:           57558            57882    +0.56%
      
      this change also improves lat_ctx from 6.69 usecs to 1.11 usec:
      
        $ ./lat_ctx -s 0 2
        "size=0k ovr=1.19
        2 1.11
      
        $ ./lat_ctx -s 0 2
        "size=0k ovr=1.22
        2 6.69
      
      in sysbench it's an overall win with some weakness at the lots-of-clients
      side. That happens because we now under-balance this workload
      a bit. To counter that effect, turn on NEWIDLE:
      
                    wake-idle          wake-idle+newidle
       -------------------------------------------------
           1:             830              834    +0.43%
           2:            1391             1401    +0.65%
           4:            3105             3091    -0.43%
           8:            6021             6046    +0.42%
          16:           10745            10736    -0.08%
          32:           10150            10206    +0.55%
          64:            9240             9533    +3.08%
         128:            8252             8355    +1.24%
         256:            8144             8384    +2.87%
       -------------------------------------------------
         SUM:           57882            58591    +1.21%
      
      as a bonus this not only improves the many-clients case but
      also improves the (more important) rampup phase.
      
      sysbench is a workload that quickly breaks down if the
      scheduler over-balances, so since it showed an improvement
      under NEWIDLE this change is definitely good.
      ea3f01f8
    • I
      revert ("sched: fair-group: SMP-nice for group scheduling") · 6363ca57
      Ingo Molnar 提交于
      Yanmin Zhang reported:
      
      Comparing with 2.6.25, volanoMark has big regression with kernel 2.6.26-rc1.
      It's about 50% on my 8-core stoakley, 16-core tigerton, and Itanium Montecito.
      
      With bisect, I located the following patch:
      
      | 18d95a28 is first bad commit
      | commit 18d95a28
      | Author: Peter Zijlstra <a.p.zijlstra@chello.nl>
      | Date:   Sat Apr 19 19:45:00 2008 +0200
      |
      |     sched: fair-group: SMP-nice for group scheduling
      
      Revert it so that we get v2.6.25 behavior.
      Bisected-by: NYanmin Zhang <yanmin_zhang@linux.intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      6363ca57
    • D
      Fix FRV minimum slab/kmalloc alignment · 0a2ce2ff
      David Howells 提交于
      > +#define	ARCH_KMALLOC_MINALIGN		(sizeof(long) * 2)
      > +#define	ARCH_SLAB_MINALIGN		(sizeof(long) * 2)
      
      This doesn't work if SLAB is selected and slab debugging is enabled as
      these are passed to the preprocessor, and the preprocessor doesn't
      understand sizeof.
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      0a2ce2ff
  6. 28 5月, 2008 5 次提交
    • D
      FRV: Specify the minimum slab/kmalloc alignment · dc1d60a0
      David Howells 提交于
      Specify the minimum slab/kmalloc alignment to be 8 bytes.  This fixes a
      crash when SLOB is selected as the memory allocator.  The FRV arch needs
      this so that it can use the load- and store-double instructions without
      faulting.  By default SLOB sets the minimum to be 4 bytes.
      Signed-off-by: NDavid Howells <dhowells@redhat.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      dc1d60a0
    • V
      MN10300: Fix typo in header guard · 5e55843b
      Vegard Nossum 提交于
      Fix a typo in the header guard of asm/ipc.h.
      Signed-off-by: NVegard Nossum <vegard.nossum@gmail.com>
      Signed-off-by: NDavid Howells <dhowells@redhat.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      5e55843b
    • J
      block: make blktrace use per-cpu buffers for message notes · 64565911
      Jens Axboe 提交于
      Currently it uses a single static char array, but that risks
      being corrupted when multiple users issue message notes at the
      same time. Make the buffers dynamically allocated when the trace
      is setup and make them per-cpu instead.
      
      The default max message size of 1k is also very large, the
      interface is mainly for small text notes. So shrink it to 128 bytes.
      Signed-off-by: NJens Axboe <jens.axboe@oracle.com>
      64565911
    • A
      Added in MESSAGE notes for blktraces · 9d5f09a4
      Alan D. Brunelle 提交于
      Allows messages to be inserted into blktrace streams.
      Signed-off-by: NAlan D. Brunelle <alan.brunelle@hp.com>
      Signed-off-by: NJens Axboe <jens.axboe@oracle.com>
      9d5f09a4
    • T
      [IA64] Workaround for RSE issue · 4dcc29e1
      Tony Luck 提交于
      Problem: An application violating the architectural rules regarding
      operation dependencies and having specific Register Stack Engine (RSE)
      state at the time of the violation, may result in an illegal operation
      fault and invalid RSE state.  Such faults may initiate a cascade of
      repeated illegal operation faults within OS interruption handlers.
      The specific behavior is OS dependent.
      
      Implication: An application causing an illegal operation fault with
      specific RSE state may result in a series of illegal operation faults
      and an eventual OS stack overflow condition.
      
      Workaround: OS interruption handlers that switch to kernel backing
      store implement a check for invalid RSE state to avoid the series
      of illegal operation faults.
      
      The core of the workaround is the RSE_WORKAROUND code sequence
      inserted into each invocation of the SAVE_MIN_WITH_COVER and
      SAVE_MIN_WITH_COVER_R19 macros.  This sequence includes hard-coded
      constants that depend on the number of stacked physical registers
      being 96.  The rest of this patch consists of code to disable this
      workaround should this not be the case (with the presumption that
      if a future Itanium processor increases the number of registers, it
      would also remove the need for this patch).
      
      Move the start of the RBS up to a mod32 boundary to avoid some
      corner cases.
      
      The dispatch_illegal_op_fault code outgrew the spot it was
      squatting in when built with this patch and CONFIG_VIRT_CPU_ACCOUNTING=y
      Move it out to the end of the ivt.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      4dcc29e1
  7. 27 5月, 2008 2 次提交
  8. 26 5月, 2008 2 次提交
  9. 25 5月, 2008 13 次提交
  10. 24 5月, 2008 1 次提交