- 15 5月, 2018 4 次提交
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由 Masahiro Yamada 提交于
It is not a good idea to directly modify the resource of a platform device. Modify its local copy, and pass it to devm_ioremap_resource() so that we do not need to restore it in the failure path and the remove hook. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NMasami Hiramatsu <mhiramat@kernel.org> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Manu Gautam 提交于
Some PHY drivers (e.g. for Qualcomm QUSB2 and QMP PHYs) support runtime PM to reduce PHY power consumption during bus_suspend. Add changes to let core auto-suspend PHYs on host bus-suspend using GUSB2PHYCFG register if needed for a platform. Also perform PHYs runtime suspend/resume and let platform glue drivers e.g. dwc3-qcom handle remote wakeup during bus suspend by waking up devices on receiving wakeup event from PHY. Signed-off-by: NManu Gautam <mgautam@codeaurora.org> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Manu Gautam 提交于
DWC3 controller on Qualcomm SOCs has a Qscratch wrapper. Some of its uses are described below resulting in need to have a separate glue driver instead of using dwc3-of-simple: - It exposes register interface to override vbus-override and lane0-pwr-present signals going to hardware. These must be updated in peripheral mode for DWC3 if vbus lines are not connected to hardware block. Otherwise RX termination in SS mode or DP pull-up is not applied by device controller. - pwr_events_irq_stat support to check if USB2 PHY is in L2 state before glue driver proceeds with suspend. - Support for wakeup interrupts lines that are asserted whenever there is any wakeup event on USB3 or USB2 bus. - Support to replace pip3 clock going to DWC3 with utmi clock for hardware configuration where SSPHY is not used with DWC3. Signed-off-by: NManu Gautam <mgautam@codeaurora.org> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Icenowy Zheng 提交于
Add compatible string to use this generic glue layer to support Allwinner H6 platform's dwc3 controller. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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- 26 3月, 2018 1 次提交
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由 Felipe Balbi 提交于
This is a requirement which has always existed but, somehow, wasn't reflected in the documentation and problems weren't found until now when Tuba Yavuz found a possible deadlock happening between dwc3 and f_hid. She described the situation as follows: spin_lock_irqsave(&hidg->write_spinlock, flags); // first acquire /* we our function has been disabled by host */ if (!hidg->req) { free_ep_req(hidg->in_ep, hidg->req); goto try_again; } [...] status = usb_ep_queue(hidg->in_ep, hidg->req, GFP_ATOMIC); => [...] => usb_gadget_giveback_request => f_hidg_req_complete => spin_lock_irqsave(&hidg->write_spinlock, flags); // second acquire Note that this happens because dwc3 would call ->complete() on a failed usb_ep_queue() due to failed Start Transfer command. This is, anyway, a theoretical situation because dwc3 currently uses "No Response Update Transfer" command for Bulk and Interrupt endpoints. It's still good to make this case impossible to happen even if the "No Reponse Update Transfer" command is changed. Reported-by: NTuba Yavuz <tuba@ece.ufl.edu> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 22 3月, 2018 12 次提交
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由 Roger Quadros 提交于
On TI's AM437x, the DWC3 controller looses state after a system suspend/resume. We are re-initializing the controller but we miss restoring the PRTCAP register. This causes USB host to break on AM437x after a system suspend/resume. Fix this by restoring the PRTCAP register on system resume. Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
DWC_usb3 speed can only be set up to SuperSpeed. Limit the setting to SuperSpeed only should the value be higher. Otherwise, the controller will read an invalid speed value and set the device to an incorrect speed. Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
Dump LSP and BMU debug info. Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure with new fields to store these threshold configurations. Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
Add new GTXTHRCFG bit field macros for DWC_usb31. The GTXTHRCFG register fields for DWC_usb31 is as follows: +-------+--------------------------+-----------------------------------+ | BITS | Name | Description | +=======+==========================+===================================+ | 31:27 | reserved | | | 26 | UsbTxPktCntSel | Async ESS transmit packet | | | | threshold enable | | 25:21 | UsbTxPktCnt | Async ESS transmit packet | | | | threshold count | | 20:16 | UsbMaxTxBurstSize | Async ESS Max transmit burst size | | 15 | UsbTxThrNumPktSel_HS_Prd | HS high bandwidth periodic | | | | transmit packet threshold enable | | 14:13 | UsbTxThrNumPkt_HS_Prd | HS high bandwidth periodic | | | | transmit packet threshold count | | 12:11 | reserved | | | 10 | UsbTxThrNumPktSel_Prd | Periodic ESS transmit packet | | | | threshold enable | | 9:5 | UsbTxThrNumPkt_Prd | Periodic ESS transmit packet | | | | threshold count | | 4:0 | UsbMaxTxBurstSize_Prd | Max periodic ESS TX burst size | +-------+--------------------------+-----------------------------------+ Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
DWC_usb31 controller has a different UsbRxPktCnt bit fields from GRXTHRCFG register. Check for DWC_usb31 IP revision to read the appropriate value. Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register fields for DWC_usb31 is as follows: +-------+--------------------------+----------------------------------+ | BITS | Name | Description | +=======+==========================+==================================+ | 31:27 | reserved | | | 26 | UsbRxPktCntSel | Async ESS receive packet | | | | threshold enable | | 25:21 | UsbRxPktCnt | Async ESS receive packet | | | | threshold count | | 20:16 | UsbMaxRxBurstSize | Async ESS Max receive burst size | | 15 | UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold enable | | 14:13 | UsbRxThrNumPkt_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold count | | 12:11 | reserved | | | 10 | UsbRxThrNumPktSel_Prd | Periodic ESS receive packet | | | | threshold enable | | 9:5 | UsbRxThrNumPkt_Prd | Periodic ESS receive packet | | | | threshold count | | 4:0 | UsbMaxRxBurstSize_Prd | Max periodic ESS RX burst size | +-------+--------------------------+----------------------------------+ Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
DWC_usb31 controller has different GTXFIFOSIZE bit field for TXFDEF. Check for DWC_usb31 IP revision to read the appropriate bit fields. Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
Update two GTXFIFOSIZ bit fields for the DWC_usb31 controller. TXFDEP is a 15-bit value instead of 16-bit value, and bit 15 is TXFRAMNUM. The GTXFIFOSIZ register for DWC_usb31 is as follows: +-------+-----------+----------------------------------+ | BITS | Name | Description | +=======+===========+==================================+ | 31:16 | TXFSTADDR | Transmit FIFOn RAM Start Address | | 15 | TXFRAMNUM | Asynchronous/Periodic TXFIFO | | 14:0 | TXFDEP | TXFIFO Depth | +-------+-----------+----------------------------------+ Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST bit is cleared, we must wait at least 50ms before accessing the PHY domain (synchronization delay). Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
Platform device is allocated before adding resources. Make sure to properly cleanup on error case. Cc: <stable@vger.kernel.org> Fixes: f1c7e710 ("usb: dwc3: convert to pcim_enable_device()") Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Felipe Balbi 提交于
If building a kernel without FTRACE but with TRACING, dwc3.ko fails to link due to missing trace events. Fix this by using the correct Kconfig symbol on Makefile. Reported-by: NRandy Dunlap <rdunlap@infradead.org> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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- 19 3月, 2018 1 次提交
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由 Heinrich Schuchardt 提交于
In dwc3_request *r = NULL; r = A; the first assignment has no effect. Remove it. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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- 13 3月, 2018 6 次提交
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由 Roger Quadros 提交于
In the following test we get stuck by sleeping forever in _dwc3_set_mode() after which dual-role switching doesn't work. On dra7-evm's dual-role port, - Load g_zero gadget driver and enumerate to host - suspend to mem - disconnect USB cable to host and connect otg cable with Pen drive in it. - resume system - we sleep indefinitely in _dwc3_set_mode due to. dwc3_gadget_exit()->usb_del_gadget_udc()->udc_stop()-> dwc3_gadget_stop()->wait_event_lock_irq() To fix this instead of waiting indefinitely with wait_event_lock_irq() we use wait_event_interruptible_lock_irq_timeout() and print and error message if there was a timeout. Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Roger Quadros 提交于
This is useful on platforms (e.g. TI AM437x) that don't have ID available on a GPIO but do have the OTG block. We can obtain the ID state via the OTG block and use it for dual-role switching. Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Roger Quadros 提交于
We don't support PRTCAP == OTG yet, so prevent user from setting it via debugfs. Fixes: 41ce1456 ("usb: dwc3: core: make dwc3_set_mode() work properly") Cc: <stable@vger.kernel.org> # v4.12+ Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Roger Quadros 提交于
Add OTG and GHWPARAMS6 register definitions Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Martin Blumenstingl 提交于
Amlogic Meson GXL and AXG SoCs come with a (host-only) dwc3 USB controller. To use this controller a clock has to be enabled and a reset line has to be pulsed. Enabling the clock works identical to other SoCs. However, the reset line has to be pulsed (using reset_control_reset) instead of using a level reset (reset_control_{assert,deassert}). Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NYixun Lan <yixun.lan@amlogic.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com> -
由 Martin Blumenstingl 提交于
Some SoCs (such as Amlogic Meson GXL for example) share the reset line with other components (in case of the Meson GXL example there's a shared reset line between the USB2 PHYs, USB3 PHYs and the dwc3 controller). Additionally SoC implementations may prefer a reset pulse over level resets. For now this falls back to the old defaults, which are: - reset lines are exclusive - level resets are being used Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NYixun Lan <yixun.lan@amlogic.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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- 08 3月, 2018 1 次提交
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由 Felipe Balbi 提交于
...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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- 28 2月, 2018 1 次提交
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由 Roger Quadros 提交于
To reproduce the lock up do the following - connect otg host adapter and a USB device to the dual-role port so that it is in host mode. - suspend to mem. - disconnect otg adapter. - resume the system. If we call dwc3_host_exit() before tasks are thawed xhci_plat_remove() seems to lock up at the second usb_remove_hcd() call. To work around this we queue the _dwc3_set_mode() work on the system_freezable_wq. Fixes: 41ce1456 ("usb: dwc3: core: make dwc3_set_mode() work properly") Cc: <stable@vger.kernel.org> # v4.12+ Suggested-by: NManu Gautam <mgautam@codeaurora.org> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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- 15 2月, 2018 1 次提交
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由 Roger Quadros 提交于
In order for ULPI PHYs to work, dwc3_phy_setup() and dwc3_ulpi_init() must be doene before dwc3_core_get_phy(). commit 541768b0 ("usb: dwc3: core: Call dwc3_core_get_phy() before initializing phys") broke this. The other issue is that dwc3_core_get_phy() and dwc3_ulpi_init() should be called only once during the life cycle of the driver. However, as dwc3_core_init() is called during system suspend/resume it will result in multiple calls to dwc3_core_get_phy() and dwc3_ulpi_init() which is wrong. Fix this by moving dwc3_ulpi_init() out of dwc3_phy_setup() into dwc3_core_ulpi_init(). Use a flag 'ulpi_ready' to ensure that dwc3_core_ulpi_init() is called only once from dwc3_core_init(). Use another flag 'phys_ready' to call dwc3_core_get_phy() only once from dwc3_core_init(). Fixes: 541768b0 ("usb: dwc3: core: Call dwc3_core_get_phy() before initializing phys") Fixes: f54edb53 ("usb: dwc3: core: initialize ULPI before trying to get the PHY") Cc: linux-stable <stable@vger.kernel.org> # >= v4.13 Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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- 12 2月, 2018 7 次提交
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由 Thinh Nguyen 提交于
The FIFO/Queue type values are incorrect. Correct them according to DWC_usb3 programming guide section 1.2.27 (or DWC_usb31 section 1.2.25). Additionally, this patch includes ProtocolStatusQ and AuxEventQ types. Fixes: cf6d867d ("usb: dwc3: core: add fifo space helper") Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Roger Quadros 提交于
The USB cable state can change during suspend/resume so be sure to check and update the extcon state. Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Manu Gautam 提交于
Commit 689bf72c ("usb: dwc3: Don't reinitialize core during host bus-suspend/resume") updated suspend/resume routines to not power_off and reinit PHYs/core for host mode. It broke platforms that rely on DWC3 core to power_off PHYs to enter low power state on system suspend. Perform dwc3_core_exit/init only during host mode system_suspend/ resume to addresses power regression from above mentioned patch and also allow USB session to stay connected across runtime_suspend/resume in host mode. While at it also replace existing checks for HOST only dr_mode with current_dr_role to have similar core driver behavior for both Host-only and DRD+Host configurations. Fixes: 689bf72c ("usb: dwc3: Don't reinitialize core during host bus-suspend/resume") Reviewed-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NManu Gautam <mgautam@codeaurora.org> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Brian Norris 提交于
In this function, we init the USB2 and USB3 PHYs, but if soft reset times out, we don't unwind this. Noticed by inspection. Signed-off-by: NBrian Norris <briannorris@chromium.org> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
DWC3 tracks TRB counter for each ep0 direction separately. In control read transfer completion handler, the driver needs to reset the TRB enqueue counter for ep0 IN direction. Currently the driver only resets the TRB counter for control OUT endpoint. Check for the data direction and properly reset the TRB counter from correct control endpoint. Cc: stable@vger.kernel.org Fixes: c2da2ff0 ("usb: dwc3: ep0: don't use ep0in for transfers") Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Thinh Nguyen 提交于
There are 2 control endpoint structures for DWC3. However, the driver only updates the OUT direction control endpoint structure during ConnectDone event. DWC3 driver needs to update the endpoint max packet size for control IN endpoint as well. If the max packet size is not properly set, then the driver will incorrectly calculate the data transfer size and fail to send ZLP for HS/FS 3-stage control read transfer. The fix is simply to update the max packet size for the ep0 IN direction during ConnectDone event. Cc: stable@vger.kernel.org Fixes: 72246da4 ("usb: Introduce DesignWare USB3 DRD Driver") Signed-off-by: NThinh Nguyen <thinhn@synopsys.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Enric Balletbo i Serra 提交于
dwc3_of_simple_dev_pm_ops has never been used since commit a0d8c4cf ("usb: dwc3: of-simple: set dev_pm_ops"), but this commit has brought and oops when unbind the device due this sequence: dwc3_of_simple_remove -> clk_disable ... -> pm_runtime_put_sync -> dwc3_of_simple_runtime_suspend -> clk_disable (again) This double call to clk_core_disable causes a kernel oops like this: WARNING: CPU: 1 PID: 4022 at drivers/clk/clk.c:656 clk_core_disable+0x78/0x80 CPU: 1 PID: 4022 Comm: bash Not tainted 4.15.0-rc4+ #44 Hardware name: Google Kevin (DT) pstate: 80000085 (Nzcv daIf -PAN -UAO) pc : clk_core_disable+0x78/0x80 lr : clk_core_disable_lock+0x20/0x38 sp : ffff00000bbf3a90 ... Call trace: clk_core_disable+0x78/0x80 clk_disable+0x1c/0x30 dwc3_of_simple_runtime_suspend+0x30/0x50 pm_generic_runtime_suspend+0x28/0x40 This patch fixes the unbalanced clk disable call by setting the num_clocks variable to zero once the clocks were disabled. Fixes: a0d8c4cf ("usb: dwc3: of-simple: set dev_pm_ops") Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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- 29 12月, 2017 1 次提交
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由 Vivek Gautam 提交于
Adding phy calibration sequence for USB 3.0 DRD PHY present on Exynos5420/5800 systems. This calibration facilitates setting certain PHY parameters viz. the Loss-of-Signal (LOS) Detector Threshold Level, as well as Tx-Vboost-Level for Super-Speed operations. Additionally we also set proper time to wait for RxDetect measurement, for desired PHY reference clock, so as to solve issue with enumeration of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive on the controller. We are using CR_port for this purpose to send required data to override the LOS values. On testing with USB 3.0 devices on USB 3.0 port present on SMDK5420, and peach-pit boards should see following message: usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd and without this patch, should see below shown message: usb 1-1: new high-speed USB device number 2 using xhci-hcd [Also removed unnecessary extra lines in the register macro definitions] Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com> [adapted to use phy_calibrate as entry point] Signed-off-by: NAndrzej Pietrasiewicz <andrzej.p@samsung.com> Acked-by: NFelipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
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- 11 12月, 2017 5 次提交
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由 Roger Quadros 提交于
Some platforms (e.g. TI's DRA7 USB2 instance) have more trouble with the metastability workaround as it supports only a High-Speed PHY and the PHY can enter into an Erratic state [1] when the controller is set in SuperSpeed mode as part of the metastability workaround. This causes upto 2 seconds delay in enumeration on DRA7's USB2 instance in gadget mode. If these platforms can be better off without the workaround, provide a device tree property to suggest that so the workaround is avoided. [1] Device mode enumeration trace showing PHY Erratic Error. irq/90-dwc3-969 [000] d... 52.323145: dwc3_event: event (00000901): Erratic Error [U0] irq/90-dwc3-969 [000] d... 52.560646: dwc3_event: event (00000901): Erratic Error [U0] irq/90-dwc3-969 [000] d... 52.798144: dwc3_event: event (00000901): Erratic Error [U0] Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com> -
由 Vincent Pelletier 提交于
Fixes the following warnings: drivers/usb/dwc3/io.h:43:31: warning: incorrect type in argument 1 (different address spaces) drivers/usb/dwc3/io.h:43:31: expected void *base drivers/usb/dwc3/io.h:43:31: got void [noderef] <asn:2>* drivers/usb/dwc3/io.h:62:32: warning: incorrect type in argument 1 (different address spaces) drivers/usb/dwc3/io.h:62:32: expected void *base drivers/usb/dwc3/io.h:62:32: got void [noderef] <asn:2>* This fixes the noisiest ones as they get emitted multiple times. A few warnings remain, for which the proper fix is less clear. No behaviour change is expected. Signed-off-by: NVincent Pelletier <plr.vincent@gmail.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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由 Felipe Balbi 提交于
Instead of keeping our own isoch_delay, let's make use of the newly introduced isoch_delay member in struct usb_gadget. The benefit here is that we would be using a generic "API" which other UDCs can use, resulting in a common setup for gadget drivers who may be interested in Isoch Delay value. Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com> -
由 Felipe Balbi 提交于
We were missing U1, U2 and LTM Enable features. Let's decode them. Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com> -
由 Manu Gautam 提交于
For isochronous endpoints with ep->mult less than 3, PCM1 value of trb->size in set incorrectly. For ep->mult = 2, this is set to 0/-1 and for ep->mult = 1, this is set to -2. This is because the initial mult is set to ep->mult - 1 instead of 2. Signed-off-by: NManu Gautam <mgautam@codeaurora.org> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
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