It is okay for both _PAGE_GUARDED and _PAGE_COHERENT (G and M) to be set
in the same pte.  In fact, even if that were not the case, there doesn't
seem to be any place where G is set without also setting I (_PAGE_NO_CACHE),
so the test for I is sufficient as a condition to clear _PAGE_COHERENT
when filling the hash table.
Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

Background from Maynard Johnson:
As of POWER6, a set of 32 common events is defined that must be
supported on all future POWER processors.  The main impetus for this
compat set is the need to support partition migration, especially from
processor P(n) to processor P(n+1), where performance software that's
running in the new partition may not be knowledgeable about processor
P(n+1).  If a performance tool determines it does not support the
physical processor, but is told (via the
PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports
the notion of the PMU compat set, then the performance tool can
surface just those events to the user of the tool.

PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at
least this basic subset of events which is compatible across POWER
processor lines.
Signed-off-by: NNathan Lynch <ntl@pobox.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

Adds a character driver for BSR support on IBM POWER systems including
Power5 and Power6.  The BSR is an optional processor facility not currently
implemented by any other processors.  It's primary purpose is fast large SMP
synchronization.  More details on the BSR are in comments to the code which
follows.  This patch adds BSR driver to pseries_defconfig.
Signed-off-by: NSonny Rao <sonnyrao@linux.vnet.ibm.com>
Signed-off-by: NJoel Schopp <jschopp@austin.ibm.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

delete obsolete device-type property, delete model property
(use compatible property instead), prepend "fsl," to Freescale
specific properties. Add nodes to device trees that are missing them,
and fix broken property values in other trees.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Remove the "uninitialized use" compile warning and avoid potential
runtime issue.
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

There isn't any reason at this point that we can't build 82xx, 83xx & 86xx
support in with the other 6xx based boards.  Twiddle the Kconfigs to allow
this.

This allows us to remove the machine type selection for related to 6xx.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Publish the devices listed in dts under SOC as of_device for 85xx_cds
platform. The devices are needed by the 85xx EDAC driver.
Signed-off-by: NDave Jiang <djiang@mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

For some reason long ago I decided that we should zero out the time base
when we calibrate the decrementer.  The problem is that this can be
harmful in SMP systems where the firmware has already synchronized the
time bases on the various cores.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Moved the pic initialization into its own common file and out of the board
code.  Also fixed the OF reference counting on the mpic node.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Initialize I2C pins on boards with CPM1/CPM2 controllers and document the
i2c bus in booting-without-of.

The boards don't have any I2C chips connected to the I2C bus, so unless
some external chips are connected to the boards, this code is just an
example of setting everything else up.
Signed-off-by: NJochen Friedrich <jochen@scram.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for the MPC8536 process and MPC8536DS reference board.  The
MPC8536 is an e500v2 based SoC which eTSEC, USB, SATA, PCI, and PCIe.

The USB and SATA IP blocks are similiar to those on the PQ2 Pro SoCs and
thus use the same drivers.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

These issues were reported by Stephen Rothwell for another 85xx board
port and pointed out by Chen Gong as issues in the DS port.

* mpic OF node reference counting was off
* of_device_id struct should be marked as __initdata
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

udbg_putc is a *function pointer* that is initialized during
udbg_init_cpm. It might not be initialized properly when called from
udbg_putc_cpm(), so (recursively) call udbg_putc_cpm() directly.
Signed-off-by: NNye Liu <nyet@mrv.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

It adds the missing RTC node to tqm8548.dts and enables support for
I2C, DS1307 and LM75 in the default configuration.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

i8259 PIC is disabled on MPC8610HPCD, and ULi IDE is configured to use
PCI sideband interrupt that is specified in the device tree.

Current HPCD's device tree specify that IDE interrupt is low to high
sensitive, but in practice ULi IDE throws active-high interrupts (not
active-low as all normal PCI devices).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Fix interrupt threading issue on pq2fads when running with CONFIG_PREEMPT_RT
Signed-off-by: NRune Torgersen <runet@innovsys.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Rename MPIC label to mpic to match all other 85xx .dts and to fix compile
issue introduced by addition of the DMA node.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add a interrupt host for the interrupt controller in the mpc5121ads cpld.
PCI interrupts are 0-7 the rest are 8-15 Touchscreen pendown irq is
hardwired to irq1 All other irqs are chained to irq0
Signed-off-by: NJohn Rigby <jrigby@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Move shared code from mpc5121_ads.c to new file mpc512x_shared.c
- mpc512x_find_ips_freq -> unchanged
- contents of mpc5121_ads_init_IRQ -> mpc512x_init_IRQ
  - looking for fsl,mpc5121-ipic instead of fsl,ipic
- mpc5121_ads_declare_of_platform_devices -> mpc5121_declare_of_platform_devices
  - and use compatible for lookup instead of node name

Add new generic board setup mpc5121_generic.c
Signed-off-by: NJohn Rigby <jrigby@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Plugs into the generic powerpc clock driver in
arch/powerpc/kernel/clock.c

The following subset of clk_interface is implemented:
    clk_get, clk_put:  get clock via name, release clock
    clk_enable, clk_disable:  enable or disable clock
    clk_get_rate:  get clock rate in Hz
    clk_set_rate:  stubbed
    clk_round_rate:  stubbed
    clk_set_parent: NULL
    clk_get_parent: NULL
Signed-off-by: NJohn Rigby <jrigby@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Current device tree is only bare bones.  This patch adds nodes to make
it a complete tree for the MPC5121ads.

Added nodes include:
    mbx      - opengl coprocessor
    nfc      - nand flash controller
    cpld-pic - on board cpld
    rtc
    clock    - clock control
    pmc      - power management control
    gpio
    mscan    - can module
    i2c
    axe      - audio coprocessor
    display  - display interface unit
    mdio
    ethernet
    usb
    ioctl    - pin config
    pata
    ac97     - PSC configured as AC97
    pscfifo  - psc fifo configuration
    dma
    pci

Fix typo in header changing MDS to ADS.

Add a compatible property of the form "fsl,mpc5121-..."
to nodes missing one.

Changed localbus compatible to fsl,mpc5121-localbus, this does
not break anything because the only code that uses it finds it
via the node name, not compatible.
Signed-off-by: NJohn Rigby <jrigby@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Fix for the following compiler warnings:

  CC      arch/powerpc/sysdev/bestcomm/bestcomm.o
  arch/powerpc/sysdev/bestcomm/bestcomm.c: In function 'mpc52xx_bcom_probe':
  arch/powerpc/sysdev/bestcomm/bestcomm.c:446:
      warning: format '%08lx' expects type 'long unsigned int',
      but argument 2 has type 'phys_addr_t'
  CC      arch/powerpc/sysdev/bestcomm/sram.o
  arch/powerpc/sysdev/bestcomm/sram.c: In function 'bcom_sram_init':
  arch/powerpc/sysdev/bestcomm/sram.c:89:
      warning: format '%08lx' expects type 'long unsigned int',
      but argument 3 has type 'phys_addr_t'
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Simplify the interface for setting up bestcomm DMA to PSCs by adding
some helper functions.  The helper function sets the correct values
for the initator and ipr values in PSC DMA tasks based on the PSC
number.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch adds the still missing FDT nodes for the MSCAN devices for
the TQM52xx modules.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Convert i2c-mpc to an of_platform driver. Utilize the code in
drivers/of-i2c.c to make i2c modules dynamically loadable by the
device tree.
Signed-off-by: NJon Smirl <jonsmirl@gmail.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

On MPC5200 the PCI target control register (PCITCR) @ MBAR + 0xD6C is
initialized with only bit 7 (Latrule disable) set. The 8-Bit write
combine timer (Bits 24..31) should be also set to a reasonable value
_greater zero_ (0x08 = default) since setting it to 0x00 leads to
_very poor_ performance as a PCI target since external burst won't be
possible at all.

Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance.
Signed-off-by: NAndre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch enables 32bit PPC's (with 36bit physical address space, e.g.
IBM/AMCC PPC44x) to run with >= 4GB of RAM. Mostly its just replacing types
(unsigned long -> phys_addr_t).

Tested on an AMCC Katmai with 4GB of DDR2.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Add the virtex and sam440ep platforms to the multiboard defconfig
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Allow the Rev A Warp boards to boot from NAND.
Signed-off-by: NSean MacLennan <smaclennan@pikatech.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This is some preliminary work to improve TLB management on SW loaded
TLB powerpc platforms. This introduce support for non-atomic PTE
operations in pgtable-ppc32.h and removes write back to the PTE from
the TLB miss handlers. In addition, the DSI interrupt code no longer
tries to fixup write permission, this is left to generic code, and
_PAGE_HWWRITE is gone.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

It is inconvenient to add additional default targets to the bootwrapper
Makefile for each new board supported which just needs a different dts
file.  This change allows the defconfig to specify additional build
targets.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

The following patch restores the PERR and SERR bits in the PCI
command register during an EEH device recovery. We have found
at least one case (an Agilent test card) where the PERR/SERR
bits are set to 1 by firmware at boot time, but are not restored
to 1 during EEH recovery.  The patch fixes the Agilent card
problem.  It has been tested on several other EEH-enabled cards
with no regressions.
Signed-off-by: NMike Mason <mmlnx@us.ibm.com>
Acked-by: NLinas Vepstas <linasvepstas@gmail.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

regs is not used in emulate_fp_pair so remove it.
Signed-off-by: NMichael Neuling <mikey@neuling.org>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

When the ucontext changed to add the VSX context, this broke backwards
compatibly on swapcontext.  swapcontext only compares the ucontext size
passed in from the user to the new kernel ucontext size.

This adds a check against the old ucontext size (with VMX but without
VSX).  It also adds some sanity check for ucontexts without VSX, but
where VSX is used according the MSR.  Fixes for both 32 and 64bit
processes on 64bit kernels

Kudos to Paulus for noticing.
Signed-off-by: NMichael Neuling <mikey@neuling.org>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

Choose a more meaningful name for better System.map readability and
autopsy value etc.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

Various instances of the EMAC core have varying: 1) number of address
match slots, 2) width of the registers for handling address match slots,
3) number of registers for handling address match slots and 4) base
offset for those registers.

As the driver stands today, it assumes that all EMACs have 4 IAHT and
GAHT 32-bit registers, starting at offset 0x30 from the register base,
with only 16-bits of each used for a total of 64 match slots.

The 405EX(r) and 460EX now use the EMAC4SYNC core rather than the EMAC4
core. This core has 8 IAHT and GAHT registers, starting at offset 0x80
from the register base, with ALL 32-bits of each used for a total of
256 match slots.

This adds a new compatible device tree entry "emac4sync" and a new,
related feature flag "EMAC_FTR_EMAC4SYNC" along with a series of macros
and inlines which supply the appropriate parameterized value based on
the presence or absence of the EMAC4SYNC feature.

The code has further been reworked where appropriate to use those macros
and inlines.

In addition, the register size passed to ioremap is now taken from the
device tree:

	c4 for EMAC4SYNC cores
	74 for EMAC4 cores
	70 for EMAC cores

rather than sizeof (emac_regs).

Finally, the device trees have been updated with the appropriate compatible
entries and resource sizes.

This has been tested on an AMCC Haleakala board such that: 1) inbound
ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11
and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from
'haleakala.local' to those same systems in the '.local' domain via MDNS
now work.
Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
Acked-by: NJeff Garzik <jgarzik@pobox.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

The current low level hash code on LPAR configurations clears
_PAGE_COHERENT (M) when either _PAGE_GUARDED (G) or _PAGE_NO_CACHE (I)
is set. This conflicts with _PAGE_SAO which has M, I and W bits sets at
once (normally invalid combo) to indicate the new SAO attribute.

This changes the code to allow that case.
Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

Allow an application to enable Strong Access Ordering on specific pages of
memory on Power 7 hardware. Currently, power has a weaker memory model than
x86. Implementing a stronger memory model allows an emulator to more
efficiently translate x86 code into power code, resulting in faster code
execution.

On Power 7 hardware, storing 0b1110 in the WIMG bits of the hpte enables
strong access ordering mode for the memory page.  This patchset allows a
user to specify which pages are thus enabled by passing a new protection
bit through mmap() and mprotect().  I have defined PROT_SAO to be 0x10.
Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

This changes the oops and backtrace code to use the new %pS
printk extension to print out symbols rather than manually
calling print_symbol.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>