1. 19 6月, 2012 3 次提交
    • V
      ARM: OMAP AM33xx: powerdomains: add AM335x support · 3f0ea764
      Vaibhav Hiremath 提交于
      Add offset & mask fields to struct powerdomain
      
      In case of AM33xx family of devices, there is no consistency between
      PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
      
      PRM_XXX           PWRSTCTRL     PWRSTST
      =======================================
      PRM_PER_MOD:      0x0C,         0x08
      PRM_WKUP_MOD:     0x04,         0x08
      PRM_MPU_MOD:      0x00,         0x04
      PRM_DEVICE_MOD:   NA,           NA
      
      And also, there is no consistency between bit-offsets inside
      PWRSTCTRL & PWRSTST register, for example -
      
      PRM_XXX           LOGICRET  MEMON  MEMRET
      =======================================
      GFX_PWRCTRL:      2,        17,    6
      PER_PWRCTRL:      3,        25,    29
      MPU_PWRCTRL:      2,        18,    22
      WKUP_PWRCTRL:     3,        NA,    NA
      
      This means, we need to maintain and pass on all this information
      in powerdomain handle; so adding fields for,
         - PWRSTCTRL/ST register offset
         - Logic retention state mask
         - mem_on/ret/pwrst/retst mask
      
      Currently, this fields is only applicable and used for AM33XX devices.
      Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
      Cc: Benoit Cousson <b-cousson@ti.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
       struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
       Add powerdomain & PRM support"; updated for 3.5]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      3f0ea764
    • V
      ARM: OMAP AM33xx: CM: Introduce AM33xx CM APIs and register level details · f969a6dc
      Vaibhav Hiremath 提交于
      As far as PRM/CM/PRCM modules are concerned, AM33XX device is
      different than OMAP3 and OMAP4 architectures; so similar to
      PRM implementation, handle AM33XX CM separately.
      
      This patch introduces AM33XX CM module low-level api's, used and
      required by omap clockdomain and hwmod framework.
      
      Please note that cm-regbits-33xx.h (register bit field offset)
      and cm33xx.h (register addr offset) files are mostly auto generated.
      Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
      Signed-off-by: NAfzal Mohammed <afzal@ti.com>
      Signed-off-by: NVaibhav Bedia <vaibhav.bedia@ti.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      CC: Tony Lindgren <tony@atomide.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Benoit Cousson <b-cousson@ti.com>
      [paul@pwsan.com: split the hwmod code changes in this patch into a separate
       patch; updated for 3.5]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      f969a6dc
    • V
      ARM: OMAP AM33xx: PRM: add PRM support · ddd04b98
      Vaibhav Hiremath 提交于
      As far as PRM/CM/PRCM modules are concerned, AM33XX device is
      different than OMAP3 and OMAP4 architectures; so we need to handle it
      separately.  This patch adds support for the PRM APIs required for
      AM33XX device.
      Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
      Signed-off-by: NAfzal Mohammed <afzal@ti.com>
      Cc: Benoit Cousson <b-cousson@ti.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Kevin Hilman <khilman@ti.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: separated the PRM parts of "ARM: OMAP3+: am33xx: Add
       powerdomain & PRM support" into this patch; fixed Makefile prm33xx.o
       location; cleaned up some checkpatch violations; updated for 3.5]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      ddd04b98
  2. 18 6月, 2012 2 次提交
  3. 05 6月, 2012 2 次提交
  4. 02 6月, 2012 5 次提交
  5. 01 6月, 2012 15 次提交
  6. 31 5月, 2012 2 次提交
  7. 30 5月, 2012 1 次提交
  8. 25 5月, 2012 2 次提交
  9. 24 5月, 2012 2 次提交
  10. 22 5月, 2012 6 次提交