- 15 3月, 2018 1 次提交
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由 Oak Zeng 提交于
This is preparation for sharing client ID definitions between amdgpu and amdkfd Signed-off-by: NOak Zeng <Oak.Zeng@amd.com> Reviewed-by: NChunming Zhou <david1.zhou@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 20 2月, 2018 7 次提交
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由 Christian König 提交于
Stuffing the PASID mapping into the VM flush isn't flexible enough since the PASID mapping changes not as often as we need a VM flush. v2: add missing use of gmc_v7_0_emit_pasid_mapping Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Keep that at a common place instead of spread over all engines. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NFelix Kuehling <felix.kuehling@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Add emit_reg_wait implementation for VCE v4. v2: call new function directly from existing code Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NFelix Kuehling <felix.kuehling@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Unify tlb flushing for gmc v9. Signed-off-by: NChristian König <christian.koenig@amd.com> Acked-by: NChunming Zhou <david1.zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Needed for vm_flush unification. Signed-off-by: NChristian König <christian.koenig@amd.com> Acked-by: NChunming Zhou <david1.zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
rd the pasid from the VM code to the emit_vm_flush function and update all implementations with the new parameter. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NChunming Zhou <david1.zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
And rename it to struct gmc_funcs. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NSamuel Li <Samuel.Li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 28 12月, 2017 1 次提交
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由 Christian König 提交于
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NChunming Zhou <david1.zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 13 12月, 2017 2 次提交
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由 Frank Min 提交于
this fix the VCE world switch hang issue Signed-off-by: NFrank Min <Frank.Min@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
And also provide the level for which we need a PDE. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NChunming Zhou <david1.zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 12月, 2017 1 次提交
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由 Shaoyun Liu 提交于
Remove the header where it's not used. Acked-by: NChristian Konig <christian.koenig@amd.com> Signed-off-by: NShaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 07 12月, 2017 4 次提交
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由 Frank Min 提交于
1. program vce 4.0 fw with 48 bit address 2. correct vce 4.0 fw stack and date offset Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NFrank Min <Frank.Min@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Feifei Xu 提交于
Remove asic_reg/vega10 folder. Signed-off-by: NFeifei Xu <Feifei.Xu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Feifei Xu 提交于
Cleanup asic_reg/vega10/MMHUB folder. Signed-off-by: NFeifei Xu <Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Feifei Xu 提交于
Cleanup asic_reg/vega10/VCE folder. Signed-off-by: NFeifei Xu <Feifei.Xu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 27 9月, 2017 1 次提交
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由 Leo Liu 提交于
Requested by SRIOV, the clearance of the bit moved into firmware Signed-off-by: NLeo Liu <leo.liu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 16 8月, 2017 5 次提交
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由 Frank Min 提交于
Optimize init table sequence for sriov. Signed-off-by: NFrank Min <Frank.Min@amd.com> Signed-off-by: NXiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Frank Min 提交于
Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff Signed-off-by: NFrank Min <Frank.Min@amd.com> Signed-off-by: NXiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Frank Min 提交于
Interrupt enable is contained in vce init table and this register could not be accessed in secure ASICs, so just remove it. Signed-off-by: NFrank Min <Frank.Min@amd.com> Signed-off-by: NXiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Frank Min 提交于
Add uvd and vce re-init after gpu reset. Signed-off-by: NFrank Min <Frank.Min@amd.com> Signed-off-by: NXiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Frank Min 提交于
MMSCH FW need to get the wptr from 0 after it get the mailbox request from driver, since every time kick the mailbox, mmsch thinks that it is the first time engine start to initialize. Signed-off-by: NFrank Min <Frank.Min@amd.com> Signed-off-by: NXiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 6月, 2017 1 次提交
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由 Leo Liu 提交于
We are using PSP to resume firmware after suspend, and it is resumed at where it got suspended, so we'd better save the the context. Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 01 6月, 2017 1 次提交
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由 Christian König 提交于
Rename adjust_mc_addr to get_vm_pde and check the address bits in one place. v2: handle vcn as well, keep setting the valid bit manually, add a BUG_ON() for GMC v6, v7 and v8 as well. v3: handle vcn_v1_0_enc_ring_emit_vm_flush as well. v4: fix the BUG_ON mask for GFX6-8 Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 25 5月, 2017 3 次提交
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由 Christian König 提交于
That GFX9 needs a PDE in the registers is entirely GFX9 specific. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NChunming Zhou <david1.zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Frank Min 提交于
According to HW design, need to clean doorbell after setup MMSCH table. Signed-off-by: NFrank Min <Frank.Min@amd.com> Signed-off-by: NXiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: NMonk Liu <Monk.Liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Trigger Huang 提交于
On vega10, some hw finish operations should not be applied in SR-IOV case. This works as workaround to fix multi-VFs reboot/shutdown issues. Signed-off-by: NTrigger Huang <trigger.huang@amd.com> Reviewed-by: NXiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: NMonk Liu <monk.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 29 4月, 2017 7 次提交
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由 Xiangliang Yu 提交于
Used virt_alloc_mm_table function to allocate MM table memory. Signed-off-by: NXiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Frank Min 提交于
Move mm table construction functions into mmsch header file so that UVD can reuse it. Signed-off-by: NFrank Min <Frank.Min@amd.com> Signed-off-by: NXiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Daniel Wang 提交于
Fixed PSP loading issue for sriov. Signed-off-by: NDaniel Wang <Daniel.Wang2@amd.com> Signed-off-by: NXiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
For Vega10 we have 18 VM invalidation engines for each VMHUB. Start to assign them manually to the rings. v2: add a BUG_ON if we use to many engines Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NAndres Rodriguez <andresx7@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Drop invalidating both hubs from each engine. v2: don't use hardcoded values Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NAndres Rodriguez <andresx7@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
Add the info which ring belonging to which VMHUB. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NAndres Rodriguez <andresx7@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Frank Min 提交于
Update the initialization sequence of VCE to make VCE work. Signed-off-by: NFrank Min <Frank.Min@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 07 4月, 2017 1 次提交
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由 Christian König 提交于
The two hubs are just instances of the same hardware, so the register bits are identical. v2: keep the function pointer Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 05 4月, 2017 1 次提交
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由 Rex Zhu 提交于
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 3月, 2017 4 次提交
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由 Harry Wentland 提交于
Signed-off-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiangliang Yu 提交于
For MM sriov, need use MMSCH to init engine and the init procedures are all saved in mm table. Signed-off-by: NXiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: NMonk Liu <Monk.Liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiangliang Yu 提交于
Allocate MM table for sriov device. Signed-off-by: NXiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: NMonk Liu <Monk.Liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NMonk Liu <Monk.Liu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiangliang Yu 提交于
VCE SRIOV need use doorbell and only works on VCN0 ring now Signed-off-by: NXiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: NMonk Liu <Monk.Liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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