1. 04 5月, 2005 19 次提交
  2. 01 5月, 2005 2 次提交
  3. 26 4月, 2005 19 次提交
    • J
      From: jbarnes@sgi.com · 605036cf
      Jesse Barnes 提交于
      [IA64] fix ia64 Kconfig to allow CONFIG_PM on sn2
      
      This probably should have been fixed when I fixed up the generic build for
      discontig+numa machines, but oh well.
      
      CONFIG_PM is allowable for generic builds but not for sn2 builds, which
      doesn't make much sense, and in fact breaks the build if recent ACPI bits are
      added to the tree.  It looks like the only arch that needs to prevent
      CONFIG_PM stuff is the ski simulator (though those options could probably use
      some cleanup as well), so remove the big conditional and replace it with a
      simple test for IA64_HP_SIM instead.
      Signed-off-by: NJesse Barnes <jbarnes@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      605036cf
    • K
      [IA64] iosapic.c: typo ... s/spin_unlock_irq/spin_unlock/ · b9e41d7f
      Kenji Kaneshige 提交于
      vector sharing patch had a typo ... mismatched spin_lock() with
      a spin_unlock_irq().  Fix from Kenji Kaneshige.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      b9e41d7f
    • T
      [IA64] print "siblings" before {physical,core,thread} id · e1ed81ab
      Tony Luck 提交于
      Rohit and Suresh changed their mind about the order to print things
      in /proc/cpuinfo, but didn't include the change in the version of
      the patch they sent to me.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      e1ed81ab
    • K
      [IA64] vector sharing (Large I/O system support) · 24eeb568
      Kenji Kaneshige 提交于
      Current ia64 linux cannot handle greater than 184 interrupt sources
      because of the lack of vectors. The following patch enables ia64 linux
      to handle greater than 184 interrupt sources by allowing the same
      vector number to be shared by multiple IOSAPIC's RTEs. The design of
      this patch is besed on "Intel(R) Itanium(R) Processor Family Interrupt
      Architecture Guide".
      
      Even if you don't have a large I/O system, you can see the behavior of
      vector sharing by changing IOSAPIC_LAST_DEVICE_VECTOR to fewer value.
      Signed-off-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      24eeb568
    • S
      [IA64] multi-core/multi-thread identification · e927ecb0
      Suresh Siddha 提交于
      Version 3 - rediffed to apply on top of Ashok's hotplug cpu
      patch.  /proc/cpuinfo output in step with x86.
      
      This is an updated MC/MT identification patch based on the 
      previous discussions on list. 
      
      Add the Multi-core and Multi-threading detection for IPF.
        - Add new core and threading related fields in /proc/cpuinfo.
      		Physical id
      		Core id
      		Thread id
      		Siblings
        - setup the cpu_core_map and cpu_sibling_map appropriately
        - Handles Hot plug CPU
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NGordon Jin <gordon.jin@intel.com>
      Signed-off-by: NRohit Seth <rohit.seth@intel.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      e927ecb0
    • K
      [IA64] __copy_user breaks on unaligned src · 6118ec84
      Keith Owens 提交于
      memcpy_mck.S::__copy_user breaks in the prefetch code under these conditions :-
      
      * src is unaligned and
      * dst is near the end of a page and
      * the page after dst is unmapped.
      Signed-off-by: NKeith Owens <kaos@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      6118ec84
    • T
      [IA64] Need to handle lfetch in "no_context" case. · f0a8d3c9
      Tony Luck 提交于
      Thanks to Mark for tracking down this one.  Users of __copy_from_user_inatomic()
      will be sad if we don't handle lfetch faults for the "no_context" case.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      f0a8d3c9
    • M
      [IA64-SGI] Altix SN add support for slots in geoid_t locator · 0985ea8f
      Mark Goodwin 提交于
      This patch against ia64-test-2.6.12 is needed for forthcoming
      Altix chipsets. It renames geoid_any_t to geoid_common_t and
      splits the 8bit 'slab' field into two 4bit fields for 'slab'
      and 'slot'. Similar changes in the Altix SAL will retain backward
      compatibility for old kernels.
      Signed-off-by: NMark Goodwin <markgw@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      0985ea8f
    • D
      [IA64] fix syscall-optimization goof · a37d98f6
      David Mosberger-Tang 提交于
      Sadly, I goofed in this syscall-tuning patch:
      
      ChangeSet 1.1966.1.40 2005/01/22 13:31:05 davidm@hpl.hp.com
        [IA64] Improve ia64_leave_syscall() for McKinley-type cores.
      
        Optimize ia64_leave_syscall() a bit better for McKinley-type cores.
        The patch looks big, but that's mostly due to renaming r16/r17 to r2/r3.
        Good for a 13 cycle improvement.
      
      The problem is that the size of the physical stacked registers was
      loaded into the wrong register (r3 instead of r17).  Since r17 by
      coincidence always had the value 1, this had the effect of turning
      rse_clear_invalid into a no-op.  That poses the risk of leaking kernel
      state back to user-land and is hence not acceptable.
      
      The fix below is simple, but unfortunately it costs us about 28 cycles
      in syscall overhead. ;-(
      
      Unfortunately, there isn't much we can do about that since those
      registers have to be cleared one way or another.
      
      	--david
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      a37d98f6
    • R
      [IA64-SGI] Shub2 BTE support - BTE recovery code · 93a07d0a
      Russ Anderson 提交于
      patch 2:
      	Shub2 BTE recovery code will be implemented in SAL.  
      	Define the SAL interface.
      	Modify bte_error to call SAL for shub2.
      Signed-off-by: NRuss Anderson <rja@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      93a07d0a
    • R
      [IA64-SGI] Add new MMR definitions/Modify BTE initialiation&copy. · 95ff439a
      Russ Anderson 提交于
      patch 1:
      	Add new MMR definitions.
      	Modify BTE initialiation.
      	Modify BTE copy.
      Signed-off-by: NRuss Anderson <rja@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      95ff439a
    • M
      [IA64-SGI] disable TIOCA GART TLB prefetching · 4628d7ca
      Mark Maule 提交于
      Patch to disable SGI TIOCA GART TLB prefetching due to hw bug.
      Signed-off-by: NMark Maule <maule@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      4628d7ca
    • T
      [IA64] MAX_PGT_FREES_PER_PASS must be 'L' to avoid warning · e96c9b47
      Tony Luck 提交于
      'min' is very picky about types of arguments, make it happy
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      e96c9b47
    • A
      [IA64] sba_iommu bug fixes · 5f6602a1
      Alex Williamson 提交于
         This fixes a couple of bugs in the zx1/sx1000 sba_iommu.  These are
      all pretty low likelihood of hitting.  The first problem is a simple off
      by one, deep in the sba_alloc_range() error path.  Surrounding that was
      a lock ordering problem that could have potentially deadlocked with the
      order the locks are grabbed in sba_unmap_single().  I moved the resource
      locking into sba_search_bitmap() to prevent this.  Finally, there's a
      potential race between unmapping pdir entries and marking incoming DMA
      pages clean.  If you see any oddities, please let me know, but I've
      tested it pretty thoroughly here.  Tony, please apply.  Thanks,
      
      BTW, many of the options in this driver not on by default are becoming
      more and more broken.  I'll be working on some patches to clean them
      out, but I wanted to get this bug fix out first.
      Signed-off-by: NAlex Williamson <alex.williamson@hp.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      5f6602a1
    • R
      [IA64] Percpu quicklist for combined allocator for pgd/pmd/pte. · fde740e4
      Robin Holt 提交于
      This patch introduces using the quicklists for pgd, pmd, and pte levels
      by combining the alloc and free functions into a common set of routines.
      This greatly simplifies the reading of this header file.
      
      This patch is simple but necessary for large numa configurations.
      It simply ensures that only pages from the local node are added to a
      cpus quicklist.  This prevents the trapping of pages on a remote nodes
      quicklist by starting a process, touching a large number of pages to
      fill pmd and pte entries, migrating to another node, and then unmapping
      or exiting.  With those conditions, the pages get trapped and if the
      machine has more than 100 nodes of the same size, the calculation of
      the pgtable high water mark will be larger than any single node so page
      table cache flushing will never occur.
      
      I ran lmbench lat_proc fork and lat_proc exec on a zx1 with and without
      this patch and did not notice any change.
      
      On an sn2 machine, there was a slight improvement which is possibly
      due to pages from other nodes trapped on the test node before starting
      the run.  I did not investigate further.
      
      This patch shrinks the quicklist based upon free memory on the node
      instead of the high/low water marks.  I have written it to enable
      preemption periodically and recalculate the amount to shrink every time
      we have freed enough pages that the quicklist size should have grown.
      I rescan the nodes zones each pass because other processess may be
      draining node memory at the same time as we are adding.
      Signed-off-by: NRobin Holt <holt@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      fde740e4
    • B
      [IA64-SGI] · ff3eb55e
      Bruce Losure 提交于
      Missed the "bk new" for this file in the last commit.
      Signed-off-by: NBruce Losure <blosure@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      ff3eb55e
    • A
      [IA64-SGI] Altix: enable poweroff · c1298c5c
      Aaron J Young 提交于
      This patch adds the necessary "hook" to allow SGI/SN
      machines to perform a system power off upon a 
      'init 0', 'halt -p', 'poweroff' or 'shutdown -h'.
      
      The "hook" is to set the pm_power_off callback
      to ia64_sn_power_down(). pm_power_off is checked
      in machine_power_off()/do_poweroff() and, if set, is executed. 
      ia64_sn_power_down() is a function already present (but not 
      used currently) in the sn kernel.
      ia64_sn_power_down() makes a SAL call to execute the
      power off.
      Signed-off-by: NAaron J Young <ayoung@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      c1298c5c
    • B
      [IA64-SGI] Bus driver for the CX port of SGI's TIO chip. · e1e19747
      Bruce Losure 提交于
      This patch is to provide CX port infrastructure for SGI TIO-based
      h/w.   Also a 'core services' driver for SGI FPGA-based h/w.
      Signed-off-by: NBruce Losure <blosure@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      e1e19747
    • S
      [IA64] perfmon: make pfm_sysctl a global, and other cleanup · 4944930a
      Stephane Eranian 提交于
      - make pfm_sysctl a global such that it is possible
        to enable/disable debug printk in sampling formats
        using PFM_DEBUG.
      
      - remove unused pfm_debug_var variable
      
      - fix a bug in pfm_handle_work where an BUG_ON() could
        be triggered. There is a path where pfm_handle_work()
        can be called with interrupts enabled, i.e., when
        TIF_NEED_RESCHED is set. The fix correct the masking
        and unmasking of interrupts in pfm_handle_work() such
        that we restore the interrupt mask as it was upon entry.
      signed-off-by: Nstephane eranian <eranian@hpl.hp.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      4944930a