Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Omit extra messages for a memory allocation failure in these functions.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When merging A20 pinctrl support to A10 pinctrl driver, the I2C function
of PI3 is wrongly written as "i2c3" (it should be "i2c4").

Fix this typo.

Fixes: cad4e209 ("pinctrl: sunxi: add support of R40 to A10 pinctrl driver")
Reported-by: NMark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Replace the specification of data structures by variable references
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Omit an extra message for a memory allocation failure in these functions.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

pinctrl/nomadik/abx500: Delete an error message for a failed memory allocation in abx500_gpio_probe()

Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Pinctrl single should just show how many pins were found, the physical
address is already in the dev information. So let's remove the wrong
information that claims to show the physical address but really prints
a virtual address that is now hashed.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Merge tag 'sh-pfc-for-v4.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.16

  - Add CAN pin groups on RZ/G1E,
  - Add CAN and CAN FD pin groups on R-Car H3 ES2.0, and R-Car D3,
  - Add support for the new R-Car V3M SoC,
  - Add support for I2C on R-Car D3,
  - Small fixes and cleanups.

This fixes some compilation issues.

GENERIC_PINCONF and OF at least for pinconf_generic_dt_*, PINMUX at
least for pinmux_ops and GPIOLIB for at least gpio_chip.

Fixes: 23f75d7d ("pinctrl: axp209: add pinctrl features")
Reported-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The number of GPIOs is gotten from a field within the structure
referenced in the of_device.data but it was actually read before it was
retrieved, thus it was dereferencing a null pointer.

Set the number of GPIOs after retrieving of_device.data.

Fixes: e1190083 ("pinctrl: axp209: add support for AXP813 GPIOs")
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Reported-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Tested-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We generally leave the GPIO clock disabled, unless an interrupt is
requested or we're accessing IO registers. We forgot to do this for the
->get_direction() callback, which means we can sometimes [1] get
incorrect results [2] from, e.g., /sys/kernel/debug/gpio.

Enable the clock, so we get the right results!

[1] Sometimes, because many systems have 1 or mor interrupt requested on
each GPIO bank, so they always leave their clock on.

[2] Incorrect, meaning the register returns 0, and so we interpret that
as "input".
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

I work for MediaTek on maintaining the existing MediaTek SoC whose target
to home gateway such as MT7622 and MT7623 that is reusing MT2701 related
files and will keep adding support for the following such kinds of SoCs
in the future.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Reviewed-by: NBiao Huang <biao.huang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add support for pinctrl on MT7622 SoC. The IO core found on the SoC has
the registers for pinctrl, pinconf and gpio mixed up in the same register
range. However, the IO core for the MT7622 SoC is completely distinct from
anyone of previous MediaTek SoCs which already had support, such as
the hardware internal, register address map and register detailed
definition for each pin.

Therefore, instead, the driver is being newly implemented by reusing
generic methods provided from the core layer with GENERIC_PINCONF,
GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code
simplicity and rid of superfluous code. Where the function of pins
determined by groups is utilized in this driver which can help developers
less confused with what combinations of pins effective on the SoC and even
reducing the mistakes during the integration of those relevant boards.

As the gpio_chip handling is also only a few lines, the driver also
implements the gpio functionality directly through GPIOLIB.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Reviewed-by: NBiao Huang <biao.huang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since lots of MediaTek drivers had been added, it seems slightly better
for that adding cleanup for placing MediaTek pinctrl drivers under the
independent menu as other kinds of drivers usually was done.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Reviewed-by: NBiao Huang <biao.huang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add devicetree bindings for MediaTek MT7622 pinctrl driver.
Signed-off-by: NSean Wang <sean.wang@mediatek.com>
Reviewed-by: NBiao Huang <biao.huang@mediatek.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This driver consists of 2 controllers due to a hole in mapping:
-1 controller for GPIO bankA to K.
-1 controller for GPIO bankZ.
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds a list of supported STM32 SoC bindings.
Signed-off-by: NGwenael Treuveur <gwenael.treuveur@st.com>
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In case a platform only defaults a "default" set of pins, but not a
"sleep" set of pins, and this particular platform suspends and resumes
in a way that the pin states are not preserved by the hardware, when we
resume, we would call pinctrl_single_resume() -> pinctrl_force_default()
-> pinctrl_select_state() and the first thing we do is check that the
pins state is the same as before, and do nothing.

In order to fix this, decouple the actual state change from
pinctrl_select_state() and move it pinctrl_commit_state(), while keeping
the p->state == state check in pinctrl_select_state() not to change the
caller assumptions. pinctrl_force_sleep() and pinctrl_force_default()
are updated to bypass the state check by calling pinctrl_commit_state().

[Linus Walleij]
The forced pin control states are currently only used in some pin
controller drivers that grab their own reference to their own pins.
This is equal to the pin control hogs: pins taken by pin control
devices since there are no corresponding device in the Linux device
hierarchy, such as memory controller lines or unused GPIO lines,
or GPIO lines that are used orthogonally from the GPIO subsystem
but pincontrol-wise managed as hogs (non-strict mode, allowing
simultaneous use by GPIO and pin control). For this case forcing
the state from the drivers' suspend()/resume() callbacks makes
sense and should semantically match the name of the function.

Fixes: 6e5e959d ("pinctrl: API changes to support multiple states per device")
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add missing copyright and add SPDX identifier.
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the documentation for the Microsemi Ocelot pinmuxing and gpio
controller.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

According to datasheet, we should use numbers for the pin naming
instead of letters. The patch here try to fix this to keep
the consistency.

This patch should not bring any functional change.

Fixes: 83c56680 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
Suggested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The AXP813 has only two GPIOs. GPIO0 can either be used as a GPIO, an
LDO regulator or an ADC. GPIO1 can be used either as a GPIO or an LDO
regulator.

Moreover, the status bit of the GPIOs when in input mode is not offset
by 4 unlike the AXP209.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

To prepare for patches that will add support for a new PMIC that has a
different GPIO adc muxing value, add an adc_mux within axp20x_pctl
structure and use it.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

To prepare for patches that will add support for a new PMIC that has a
different GPIO input status register, add a gpio_status_offset within
axp20x_pctl structure and use it.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This driver used to do only GPIO features of the GPIOs in X-Powers
AXP20X. Now that we have migrated everything to the pinctrl subsystem
and added pinctrl features, rename everything related to pinctrl from
gpio to pctl to ease the understanding of differences between GPIO
and pinctrl features.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The X-Powers AXP209 has 3 GPIOs. GPIO0/1 can each act either as a GPIO,
an ADC or a LDO regulator. GPIO2 can only act as a GPIO.

This adds the pinctrl features to the driver so GPIO0/1 can be used as
ADC or LDO regulator.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The X-Powers AXP209 has 3 GPIOs. GPIO0/1 can each act either as a GPIO,
an ADC or a LDO regulator. GPIO2 can only act as a GPIO.

This adds the pinctrl features to the driver so GPIO0/1 can be used as
ADC or LDO regulator.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

To prepare the driver for the upcoming pinctrl features, move the GPIO
driver AXP209 from GPIO to pinctrl subsystem.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Checkpatch complains with the following message:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

Let's make it happy by switching over to unsigned int.
Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In the (unlikely) event that community->ngpps is zero, or if every
gpp->gpio_base is less than zero, then an ininitialized value in
ret is returned by function intel_gpio_add_pin_ranges. Fix this by
ensuring ret is initialized to zero.  It's a moot point, but I think
it is worthwhile ensuring this corner case is fixed.

Detected by CoverityScan, CID#1462415 ("Uninitialized scalar variable")

Fixes: a60eac32 ("pinctrl: intel: Allow custom GPIO base for pad groups")
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Gemini pin controller can set drive strength for a few
select groups of pins (not individually). Implement this
for GMAC0 and 1 (ethernet ports), IDE and PCI.

Cc: devicetree@vger.kernel.org
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds CAN FD[0-1] pinmux support to the r8a77995 SoC.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CAN[0-1] pinmux support to the r8a77995 SoC.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch renames the pin function macro definitions of the GPSR5 and
IPSR{0,3,5,6,12} registers value for the RTS{0,1,3,4}# pin.

This is a correction because GPSR and IPSR register specification for
R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>