There are general changes pending to make the /aliases/serial* entries
number the serial ports on the system. On Tegra, so far the ports have
been just numbered dynamically as they are configured so that makes them
change.

To avoid this, add specific aliases per board to keep the old numbers.
This allows us to change the numbering by default on future SoCs while
keeping the numbering on existing boards.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Ventana uses a CLAA101WA01A LCD panel. Enable the relevant display
controller, backlight, and regulators.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NThierry Reding <treding@nvidia.com>

This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.

tegra124-venice2.dts isn't touched yet since we haven't added any off-
SoC RTC device to its device tree.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use key code macros for all key code refernced for keys.

For tegra20-seaboard.dts and tegra20-harmony.dts:
  The key comment for key (16th row and 1st column) is KEY_KPSLASH but
  code is 0x004e which is the key code for KEY_KPPLUS. As there other
  key exist with KY_KPPLUS, I am assuming key code is wrong and comment
  is fine. With this assumption, I am keeping the key code as KEY_KPSLASH.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

DT node names should include a unit address iff the node has a reg
property. For Tegra DTs at least, we were previously applying a different
rule, namely that node names only needed to include a unit address if it
was required to make the node name unique. Consequently, many unit
addresses are missing. Add them.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Enabling the LP1 suspend mode for Tegra devices.

Tested-by: Marc Dietrich <marvin24@gmx.de> # paz00 board
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use the Tegra20 CAR binding header (tegra20-car.h) to replace magic
numbers in the device tree. For example,

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
[swarren, updated since tegra20-car.h moved for consistency]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use the GIC and standard IRQ binding defines in all IRQ specifiers.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties,
and some interrupts properties. Use standard GPIO flag defines too.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT
files, so that gcc -E handles the entire include tree, and hence any of
those files can #include some other file e.g. for constant definitions.

This allows future use of #defines and header files in order to define
names for various constants, such as the IDs and flags in GPIO
specifiers. Use of those features will increase the readability of the
device tree files.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch updates all Tegra board files so that they contain all the
properties required by the updated USB DT binding. Note that this patch
only adds the new properties and does not yet remove the old properties,
in order to maintain bisectability. The old properties will be removed
once the driver has been updated to assume the new bindings.
Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com>
[swarren: fixed some newly added regulator-name properties to better
match schematic, avoided duplicate regulator-name on Whistler.]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

1. All Tegra20 ULPI reset GPIO DT properties are modified to indicate active
low nature of the GPIO.
2. Placed USB PHY DT node immediately below the EHCI controller DT nodes
and corrected reg value in the name of USB PHY DT node.
Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding the PM configuration of PMC when the platform support suspend
function.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch adds "non-removable" property of MMC host where the eMMC device
is for Tegra platform.

And the "keep-power-in-suspend" property was used for the SDIO device that
need this to go into suspend mode (e.g. BRCM43xx series).
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This adds the power gpio key to DT and enable the wakeup of the gpio key
for the device. The Seaboard and paz00 already had the power gpio key
binding and the power key of Whistler was on KBC. So these boards' device
tree didn't include in this patch.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Audio-related clocks need to be represented in the device tree. Update
bindings to describe which clocks are needed, and DT files to include
those clocks.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding the bindings of the clock source of PMC in DT.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The GPIO pin of SD slot card detection should active low.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

As reset GPIO information is PHY specific detail, adding
it to PHY DT node.
Signed-off-by: NVenu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use engineering name 'Tegra20' instead of 'Tegra2'
Signed-off-by: NBryan Wu <pengw@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Harmony board has an ON Semiconductors NCT1008 temperature sensor
connected to the DVC bus. It can be used to monitor the ambient (local)
and on-die (remote) temperatures.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Tegra 2's I2C2 controller can be routed to either the PTA
or DDC pin group on Ventana. So:
- Remove the HDMI function definition of pta pingroup
- Define child i2c adapters(ddc & pta) for I2C2 controller
Signed-off-by: NMark Zhang <markz@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Configure pinmux as required for WiFi.
Enable the SDHCI1 controller, which is connectted to the WiFi module.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Commit 13511def "regulator: deprecate regulator-compatible DT property"
now allows for simpler content within the regulators node within a PMIC.
Modify all the Tegra device tree files to take advantage of this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NThierry Reding <thierry.reding@avionic-design.de>

For Seaboard, Ventana, and Cardhu, add DT property to tell the regulator
that it should provide the pm_power_off() implementation. This allows
"shutdown" to work.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Ventana uses a TPS6586x regulator. Instantiate this, and hook up a
couple of fixed GPIO-controlled regulators too.

The data was chosen to match the PMIC HW defaults, with the following
exception:

ldo6: The HW default is 2.85v. The schematics are unlabelled. Internal
research indicates that 1.8v is correct. Our downstream kernel also uses
1.8v.

Portions based on work by Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Most ARM ${board}.dts files are already named ${soc}-${board}.dts. This
change modifies the Tegra board files to be named the same way for
consistency.

Once a related change is made in U-Boot, this will cause both U-Boot and
the kernel to use the same names for the .dts files and SoC identifiers,
thus allowing U-Boot's recently added "soc" and "board" environment
variables to be used to construct the name of Tegra .dtb files, and hence
allow board-generic U-Boot bootcmd scripts to be written.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The driver supports the new bus-width property, so remove the legacy
support-8bit property.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch unifies the current DT MMC bindings documentation and code,
adds generic MMC DT bindings documentation, and updates .dts files for
consistency.

[cjb: typo fixes, addition of max-frequency property]
Signed-off-by: NChris Ball <cjb@laptop.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

In tegra*.dtsi, set status="disable" for all HW modules that the board
design may choose not to use. Update all boards to specifically enable
any of those modules that are useful by setting status="okay".

This makes board files say which features they do use, rather than which
they don't, which feels more logical. It also makes the .dts files
slightly smaller, at least for existing content.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Sort the nodes according to the following rules:
* First, any overrides for properties or nodes created by included files,
  in the order they appeared in the include file.
* Second, any nodes with a reg property, in numerical order.
* Third, any nodes without a reg property, in alphabetical order of node
  name.

The second sorting rule at least will probably help if/when we need to
explicitly insert nodes for the various busses in Tegra; that will just
be an indentation change rather than also a node re-ordering.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Ensure that all Tegraa GPIO specifiers contain a comment indicating which
GPIO name the number refers to.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

DT node names only need to include the unit address if it's required to
make the node name unique. Remove the unnecessary unit addresses.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Consistently don't place a space after < or before >.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Add the device info for ALS and proximity sensor for tegra
boards cardhu, ventana and seaboard.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: s/PZ02/PZ2/ in .dts files, s/seabridge/seaboard/ in commit
 description]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

ULPI PHYs have a reset signal, and different boards use a different GPIO
for this task. Add a property to device tree to represent this.

I'm not sure if adding this property to the EHCI controller node is
entirely correct; perhaps eventually we should have explicit separate
nodes for the various PHYs. However, we don't have that right now, so this
binding seems like a reasonable choice.

Cc: <devicetree-discuss@lists.ozlabs.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: <linux-usb@vger.kernel.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>