- 02 4月, 2006 1 次提交
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由 Lennert Buytenhek 提交于
Patch from Lennert Buytenhek This patch adds support for the I/O coherent cache available on the xsc3. The approach is to provide a simple API to determine whether the chipset supports coherency by calling arch_is_coherent() and then setting the appropriate system memory PTE and PMD bits. In addition, we call this API on dma_alloc_coherent() and dma_map_single() calls. A generic version exists that will compile out all the coherency-related code that is not needed on the majority of ARM systems. Note that we do not check for coherency in the dma_alloc_writecombine() function as that still requires a special PTE setting. We also don't touch dma_mmap_coherent() as that is a special ARM-only API that is by definition only used on non-coherent system. Signed-off-by: NDeepak Saxena <dsaxena@plexity.net> Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 22 3月, 2006 1 次提交
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由 Russell King 提交于
Read the processor ID at boot, and save it in "processor_id" as we did before. Later, when we re-parse the CPU type in the setup.c code, re-use the value stored in "processor_id". This allows a cleaner work-around for noMMU devices without CP#15. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 16 3月, 2006 2 次提交
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由 Ben Dooks 提交于
Patch from Ben Dooks arch/arm/kernel/setup.c declares mem_fclk_21285 when this is already declared in include/asm-arm/system.h Signed-off-by: NBen Dooks <ben-linux@fluff.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Ben Dooks 提交于
Patch from Ben Dooks arch/arm/kernel/compat.c exports two functions, convert_to_tag_list and squash_mem_tags which are not defined in any header files, and not used outside arch/arm/kernel. Signed-off-by: NBen Dooks <ben-linux@fluff.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 16 2月, 2006 1 次提交
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由 Russell King 提交于
A change to the SMP initialisation caused the following oops: CPU1: Booted secondary processor CPU1: D VIPT write-back cache CPU1: I cache: 32768 bytes, associativity 4, 32 byte lines, 256 sets CPU1: D cache: 32768 bytes, associativity 4, 32 byte lines, 256 sets <7>Calibrating delay loop... 83.14 BogoMIPS (lpj=415744) <1>Unable to handle kernel NULL pointer dereference at virtual address 0000001c ... PC is at enqueue_task+0x1c/0x64 LR is at activate_task+0xcc/0xe4 SMP initialisation now requires cpu_possible_map to be initialised in setup_arch(). Move this from smp_prepare_cpus() to smp_init_cpus() and call it from our setup_arch() if CONFIG_SMP is enabled. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 13 1月, 2006 1 次提交
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由 Catalin Marinas 提交于
Patch from Catalin Marinas Since ARM1176, the CPU ID format has changed and it will also be used for future ARM architectures. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 04 1月, 2006 1 次提交
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由 Russell King 提交于
arch/arm/kernel/entry-armv.S has contained a comment suggesting that asm/hardware.h and asm/arch/irqs.h should be moved into the asm/arch/entry-macro.S include. So move the includes to these two files as required. Add missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h includes which use those facilities, and remove asm/io.h from kernel/process.c. Remove other unnecessary includes from arch/arm/kernel, arch/arm/mm and arch/arm/mach-footbridge. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 07 11月, 2005 2 次提交
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由 Russell King 提交于
glibc expects to count lines beginning with "processor" to determine the number of processors, not lines beginning with "Processor". So, give glibc the format it expects. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
We don't want to call dump_cpu_info() from cpu_init() after boot since it produces a lot of unnecessary noise - since cpu_init() gets called on resume and hotplug cpu insertion events. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 04 7月, 2005 1 次提交
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由 Russell King 提交于
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 29 6月, 2005 1 次提交
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由 Catalin Marinas 提交于
Patch from Catalin Marinas The compiler allocates r14 for the stk variable in the __asm__ directive. This is a shadowed register and gets changed when the mode is changed, causing random values in the SP register. The patch adds a clobber for the r14 register. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 23 6月, 2005 1 次提交
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由 Russell King 提交于
Ensure that meminfo.bank[] array contains page-aligned start/size information. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 20 6月, 2005 1 次提交
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由 Russell King 提交于
We need to re-initialise the stack pointers for undefined, IRQ and abort mode handlers whenever we resume. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 01 6月, 2005 1 次提交
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由 Russell King 提交于
The current vector entry system does not allow for SMP. In order to work around this, we need to eliminate our reliance on the fixed save areas, which breaks the way we enable alignment traps. This patch changes the way we handle the save areas such that we can have one per CPU. Signed-off-by: NRussell King <rmk@arm.linux.org.uk>
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- 17 4月, 2005 1 次提交
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由 Linus Torvalds 提交于
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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