- 08 3月, 2018 5 次提交
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由 Shawn Guo 提交于
The power supplies to PCIe port are often controlled by GPIO on some board designs. Let's add an optional regulator which can be backed by GPIO to control the power. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NRob Herring <robh@kernel.org>
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由 Shawn Guo 提交于
If clk_prepare_enable() call fails on a particular clock, we should not call clk_disable_unprepare() on this clock, but on the clocks that succeed from clk_prepare_enable() previously. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Srinivas Kandagatla 提交于
This patch converts existing regulators to use regulator bulk apis, to make it consistent with msm8996 changes also cut down some redundant code. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com>
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由 Srinivas Kandagatla 提交于
This patch adds supplies that are required for msm8996. vdda is analog supply that go in to controller, and vddpe_3v3 is supply to PCIe endpoint. Without these supplies PCIe endpoints which require power supplies are not enumerated at all, as there is no one to power it up. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com> Reviewed-by: NRob Herring <robh@kernel.org>
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由 Niklas Cassel 提交于
Fix typo in error message. s/deb_base2/dbi_base2/ Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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- 06 3月, 2018 3 次提交
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由 Gustavo Pimentel 提交于
The Synopsys PCIe Root Complex supports up to MSI 256 IRQs distributed over 8 controller registers, therefore the maximum number of MSI IRQs can be changed to 256. The number of controllers can be calculated based on the number of vectors used by the specific SoC driver. Update the dwc host bridge driver maximum number of supported MSI IRQs. Signed-off-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: NNiklas Cassel <niklas.cassel@axis.com> Tested-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
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由 Gustavo Pimentel 提交于
Remove the unused old MSI IRQs API from pcie-designware based on struct msi_controller that should now be considered obsolete. Signed-off-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: NNiklas Cassel <niklas.cassel@axis.com> Tested-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
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由 Gustavo Pimentel 提交于
Implement a multiplexed IRQ domain hierarchy API in the pcie-designware host bridge driver that funnels all MSI IRQs into a single parent interrupt, moving away from the obsolete struct msi_controller based API. Although the old implementation API is still available, pcie-designware will now use the multiplexed IRQ domains hierarchical API. Remove all existing dwc based host bridges MSI IRQs handlers, in that the hierarchical API now handles MSI IRQs through the hierarchical/chained MSI domain implementation. Signed-off-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: NNiklas Cassel <niklas.cassel@axis.com> Tested-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NJingoo Han <jingoohan1@gmail.com> Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
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- 31 1月, 2018 2 次提交
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由 Cyrille Pitchen 提交于
This patch updates the prototype of most handlers from 'struct pci_epc_ops' so the EPC library can now support multi-function devices. Signed-off-by: NCyrille Pitchen <cyrille.pitchen@free-electrons.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Cyrille Pitchen 提交于
Clean up drivers/Makefile by moving the pci/endpoint and pci/dwc entries from drivers/Makefile into drivers/pci/Makefile. Since we don't want to introduce any dependency between CONFIG_PCI and CONFIG_PCI_ENDPOINT, we now always execute drivers/pci/Makefile. Hence all Makefiles in drivers/pci/ were updated accordingly so no file is compiled when CONFIG_PCI is not defined. Also, we add a comment to reinforce that EPC and EPF libraries must be initialized before their users. Hence built-in EPC drivers, such as those of Designware, are linked after the endpoint core libraries. Finally, we add another comment to explain why obj-y has been chosen instead of obj-$(CONFIG_PCIE_DW) to parse the dwc/ sub-folder. Signed-off-by: NCyrille Pitchen <cyrille.pitchen@free-electrons.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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- 29 1月, 2018 1 次提交
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由 Bjorn Helgaas 提交于
Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license. Remove the boilerplate GPL version 2 language, relying on the assertion in b2441318 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") that the SPDX identifier may be used instead of the full boilerplate text. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 27 1月, 2018 1 次提交
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由 Bjorn Helgaas 提交于
b2441318 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") added SPDX GPL-2.0 to several PCI files that previously contained no license information. Add SPDX GPL-2.0 to all other PCI files that did not contain any license information and hence were under the default GPL version 2 license of the kernel. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 23 1月, 2018 1 次提交
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由 Jaehoon Chung 提交于
In order to avoid triggering a NULL pointer dereference in exynos_pcie_probe() a check must be put in place to detect if the init_clk_resources hook is initialized before calling it. Add the respective function pointer check in exynos_pcie_probe(). Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> [lorenzo.pieralisi@arm.com: rewrote the commit log] Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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- 10 1月, 2018 2 次提交
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由 Vignesh R 提交于
It is possible that more than one legacy IRQ may be set at the same time, therefore iterate and handle all the pending INTx interrupts before clearing the status and exiting the IRQ handler. Otherwise, some interrupts would be lost. Signed-off-by: NVignesh R <vigneshr@ti.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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由 Vignesh R 提交于
Legacy INTD IRQ handling is broken on dra7xx due to fact that driver uses hwirq in range of 1-4 for INTA, INTD whereas IRQ domain is of size 4 which is numbered 0-3. Therefore when INTD IRQ line is used with pci-dra7xx driver following warning is seen: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:342 irq_domain_associate+0x12c/0x1c4 error: hwirq 0x4 is too large for dummy Fix this by using pci_irqd_intx_xlate() helper to translate the INTx 1-4 range into the 0-3 as done in other PCIe drivers. Suggested-by: NBjorn Helgaas <bhelgaas@google.com> Reported-by: NChris Welch <Chris.Welch@viavisolutions.com> Signed-off-by: NVignesh R <vigneshr@ti.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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- 04 1月, 2018 1 次提交
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由 Julia Lawall 提交于
This driver creates various const structures that it stores in the data field of an of_device_id array. Adding const to the declaration of the location that receives the const value from the data field ensures that the compiler will continue to check that the value is not modified. Furthermore, the const-discarding cast on the extraction from the data field is no longer needed. Done using Coccinelle. Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com>
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- 03 1月, 2018 2 次提交
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由 Wei Yongjun 提交于
In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Jaehoon Chung 提交于
Exynos platforms have a PCI PHY driver in the PHY framework that can be used by the PCI host bridge drivers to initialize and manage the PHY. Remove the deprecated PHY initialization code in the Exynos PCI host bridge driver by updating the driver to use the PHY framework API; modify the DT binding documentation accordingly. Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NJingoo Han <jingoohan1@gmail.com> Reviewed-by: NRob Herring <robh@kernel.org>
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- 21 12月, 2017 16 次提交
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由 Niklas Cassel 提交于
Add support for the ARTPEC-7 SoC in the artpec6 driver. The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar. Unfortunately, some fields in the PCIECFG and PCIESTAT register have changed. Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Niklas Cassel 提交于
Waiting for the PHY while the core was held in reset worked for artpec6, but for artpec7, in order to read the required registers, the core has to be out of reset. Refactor the code so we always wait for the PHY after the core has been deasserted, since this works for both artpec6 and artpec7. Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Niklas Cassel 提交于
The current cpu addr fixup mask for ARTPEC-6, GENMASK(27, 0), is wrong. The correct cpu addr fixup mask for ARTPEC-6 is GENMASK(28, 0). However, having a hardcoded cpu addr fixup mask in each driver is arguably wrong. A device tree property called something like "cpu-addr-fixup-mask" would have been a better solution. Introducing such a property is not needed though, since we already have pp->cfg0_base and ep->phys_base, which is derived from already existing device tree properties. It is also worth noting that for ARTPEC-7, hardcoding the cpu addr fixup mask is not possible, since it uses a High Address Bits Look Up Table, which means that it can, at runtime, map the PCIe window to an arbitrary address in the 32-bit address space. By using pp->cfg0_base and ep->phys_base, we avoid hardcoding a mask in each driver. This should work for ARTPEC-6, DRA7xx, and ARTPEC-7. I have not changed the code in DRA7xx though, since their existing code works, but if they want, they could use the same logic as artpec6_pcie_cpu_addr_fixup, and thus remove their hardcoded mask. The reason why the fixup mask is needed is explained in commit f4c55c5a ("PCI: designware: Program ATU with untranslated address"). Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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由 Niklas Cassel 提交于
The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in endpoint mode. Add endpoint mode support to the artpec6 driver. Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Niklas Cassel 提交于
Split artpec6_pcie_establish_link() into smaller functions to better match other drivers such as dra7xx and imx6. This is also done to prepare for endpoint mode support. Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Niklas Cassel 提交于
Use BIT and GENMASK macros to improve readability. Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Niklas Cassel 提交于
Commit b015b37e ("PCI: artpec6: Stop enabling writes to DBI read-only registers") removed the only write using these defines, but it did not remove the defines. Remove the defines since they are now unused. Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Niklas Cassel 提交于
The dra7xx driver supports both host and ep mode. When enabling support for only one of the modes, help the compiler to remove code for the mode that we have not enabled in the driver. By adding if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) return -ENODEV; anything after that statement will get silently dropped by the compiler, including static functions and structures that are referenced indirectly from there. Suggested-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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由 Niklas Cassel 提交于
Assign pp->ops in *_add_pcie_port() to match how it is done in other drivers like exynos, imx7, keystone, armada8k, artpec6, designware-plat, hisi, kirin and spear13xx. This is probably a remainder since when dev and ops were assigned as members to pp. Since we now assign them as members to struct dw_pcie, the pp->ops assignment should definitely be in dra7xx_add_pcie_port(). This is done so that the compiler (in a later commit) can remove more code when enabling only one of the two supported modes (host/ep) in the dra7xx driver. Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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由 Niklas Cassel 提交于
Refactor the Kconfig and Makefile handling for host/ep mode, since the previous handling was a bit unorthodox and would have been a bit bloated once more DWC based controllers added support for ep mode. Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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由 Niklas Cassel 提交于
Add a generic function for raising MSI irqs that can be used by all DWC based controllers. Note that certain controllers, like DRA7xx, have a special convenience register for raising MSI irqs that doesn't require you to explicitly map the MSI address. Therefore, it is likely that certain drivers will not use this generic function, even if they can. Tested-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NJoao Pinto <jpinto@synopsys.com>
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由 Niklas Cassel 提交于
Remove the static keyword from dw_pcie_ep_reset_bar() so that pci-dra7xx.c does not need its own copy of dw_pcie_ep_reset_bar(). Tested-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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由 Niklas Cassel 提交于
Certain SoCs need to map the MSI address in raise_irq. To map an address, you first need to call pci_epc_mem_alloc_addr(), however, pci_epc_mem_alloc_addr() calls ioremap() (which can sleep). Since raise_irq is only called from atomic context, we can't call pci_epc_mem_alloc_addr() from raise_irq. Pre-allocate a page in dw_pcie_ep_init(), so that this page can later be used to map/unmap the MSI address in raise_irq. Tested-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NJoao Pinto <jpinto@synopsys.com>
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由 Niklas Cassel 提交于
Certain registers that pcie-designware-ep tries to write to are read-only registers. However, these registers can become read/write if we first enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit before/after writing these registers. Tested-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NJoao Pinto <jpinto@synopsys.com>
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由 Niklas Cassel 提交于
Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control register, thus overwriting the PCI_MSI_FLAGS_64BIT bit. By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI on systems where the RC has set a 64 bit MSI address. Fix dw_pcie_ep_set_msi() so that it only sets MMC bits. Tested-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NJoao Pinto <jpinto@synopsys.com>
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由 Niklas Cassel 提交于
Use the DMA-API to get the MSI address. This address will be written to our PCI config space and to the register which determines which AXI address the DWC IP will spoof for incoming MSI irqs. Since it is a PCIe endpoint device, rather than the CPU, that is supposed to write to the MSI address, the proper way to get the MSI address is by using the DMA API, not by using virt_to_phys(). Using virt_to_phys() might work on some systems, but using the DMA API should work on all systems. This is essentially the same thing as allocating a buffer in a driver to which the endpoint will write to. To do this, we use the DMA API. Tested-by: NGustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NJoao Pinto <jpinto@synopsys.com>
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- 20 12月, 2017 1 次提交
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由 Vignesh R 提交于
Define dra7xx_pcie_shutdown() as a static function as it is not used in other compilation units. Signed-off-by: NVignesh R <vigneshr@ti.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: NKeerthy <j-keerthy@ti.com>
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- 19 12月, 2017 3 次提交
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由 Johan Hovold 提交于
Fix child-node lookup during initialisation which was using the wrong OF-helper and ended up searching the whole device tree depth-first starting at the parent rather than just matching on its children. To make things worse, the parent pci node could end up being prematurely freed as of_find_node_by_name() drops a reference to its first argument. Any matching child interrupt-controller node was also leaked. Fixes: 0c4ffcfe ("PCI: keystone: Add TI Keystone PCIe driver") Cc: stable <stable@vger.kernel.org> # 3.18 Acked-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NJohan Hovold <johan@kernel.org> [lorenzo.pieralisi@arm.com: updated commit subject] Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Kishon Vijay Abraham I 提交于
->get_msi() now checks MSI_EN bit in the MSI CAPABILITY register to find whether the host supports MSI instead of using the MSI ADDRESS in the MSI CAPABILITY register. This fixes the issue with the following sequence 'modprobe pci_endpoint_test' enables MSI 'rmmod pci_endpoint_test' disables MSI but MSI address (in EP's capability register) has a valid value 'modprobe pci_endpoint_test no_msi=1' - Since MSI address (in EP's capability register) has a valid value (set during the previous insertion of the module), EP thinks host supports MSI. Fixes: f8aed6ec ("PCI: dwc: designware: Add EP mode support") Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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由 Niklas Cassel 提交于
find_first_zero_bit()'s parameter 'size' is defined in bits, not in bytes. find_first_zero_bit() is called with size in bytes rather than bits, which thus defines a too low upper limit, causing dw_pcie_ep_inbound_atu() to assign iatu index #4 to both bar 4 and bar 5, which makes bar 5 overwrite the settings set by bar 4. Since the sizes of the bitmaps are known, dynamically allocate the bitmaps, and use the correct size when calling find_first_zero_bit(). Additionally, make sure that ep->num_ob_windows and ep->num_ib_windows, which are obtained from device tree, are smaller than the maximum number of iATUs (MAX_IATU_IN/MAX_IATU_OUT). Fixes: f8aed6ec ("PCI: dwc: designware: Add EP mode support") Signed-off-by: NNiklas Cassel <niklas.cassel@axis.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
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- 02 11月, 2017 1 次提交
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由 Greg Kroah-Hartman 提交于
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: NKate Stewart <kstewart@linuxfoundation.org> Reviewed-by: NPhilippe Ombredanne <pombredanne@nexb.com> Reviewed-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 25 10月, 2017 1 次提交
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由 Jianguo Sun 提交于
Add a HiSilicon STB SoC PCIe controller driver. This controller is based on the DesignWare PCIe core. Signed-off-by: NJianguo Sun <sunjianguo1@huawei.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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