Update asm/netlogic/haldefs.h to extend register access functions
nlm_{read,write}_reg64() for 32-bit compilation. When compiled for 32-bit
the functions will read 64 IO registers with interrupts disabled.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5026/Acked-by: NJohn Crispin <blogic@openwrt.org>

The index for a device interrupt in the PIC interrupt routing table
changes for different chips in the XLP family.  Avoid using the fixed
entries and derive the index value from the SoC device header.

Add workarounds for some devices which do not report the IRT index
correctly.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5025/Acked-by: NJohn Crispin <blogic@openwrt.org>

Remove the definitions of {read,write}_c0_{eirr,eimr}. These functions
are now unused after the PIC and IRQ code has been updated to use
optimized EIMR/EIRR functions which work on both 32-bit and 64-bit.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5021/Acked-by: NJohn Crispin <blogic@openwrt.org>

Remove the irq save/restore from write_c0_eimr(), as it is always called
with interrupts off.

This allows us to remove workaround in write_c0_eimr() to fix up the
flags used by local_irq_save. This fixup worked on XLR, but will break
when 32-bit support is added to r2 cpus like XLP.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5022/Acked-by: NJohn Crispin <blogic@openwrt.org>

The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC
frequencey. One of these can be used as a clocksource to provide
timestamps that is common across cores. This can be used in place
of the count/compare clocksource which is per-CPU.

On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits
of the PIC counter. On XLP, the whole 64-bit can be used.

Provide common macros and functions for PIC timer registers on XLR/XLS
and XLP, and use them to register a PIC clocksource.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4786/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Since we now use r4k cache code for Netlogic XLP, it is
better to split L1 icache among the active threads, so that
threads won't step on each other while flushing icache.

The L1 dcache is already split among the threads in the core.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4787/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr()
and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations
and update the interrupt handling code to use these functions.
Also, use the EIMR register functions to mask interrupts in the
irq code.

The 64-bit interrupt request and mask registers (EIRR and EIMR) are
accessed when the interrupts are off, and the common operations are
to set or clear a bit in these registers. Using the 64-bit c0 access
functions for these operations is not optimal in 32-bit, because it
will disable/restore interrupts and split/join the 64-bit value during
each register access.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4790/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

On XLR/XLS, the cpu cores communicate with fast on-chip devices
(e.g. network accelerator, security engine etc.) using the Fast
Messaging Network(FMN). The FMN queues and credits needs to be
configured and intialized before it can be used.

The co-processor 2 on XLR/XLS CPU cores has registers for FMN access,
and the XLR/XLS has custom instructions for sending and loading
messages.  The FMN can deliver also per-cpu interrupts when messages
are available at the CPU.

This patch adds FMN initialization, adds interrupt setup and handling,
and also provides support for sending and receiving FMN messages.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4468Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Create struct nlm_pic_irq for interrupts handled by the PIC.
This simplifies IRQ handling for multi-SoC as well as
the single SoC cases. Also split the setup of percpu and PIC
interrupts so that we can configure the PIC interrupts for
every node.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4467Signed-off-by: NJohn Crispin <blogic@openwrt.org>

There can be 1, 2 or 4 SoCs(nodes) in a multi-chip XLP board. Add an
option for multi-chip boards in case of XLP, and make the number of
nodes configurable.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4470Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Upto 4 Netlogic XLP SoCs can be connected over ICI links to form a
coherent multi-node system.  Each SoC has its own set of on-chip
devices including PIC.  To support this, add a per SoC stucture and
use it for the PIC and SYS block addresses instead of using global
variables.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4469Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Initial code to support more than 32 cpus. The platform CPU mask
is updated from 32-bit mask to cpumask_t. Convert places that use
cpu_/cpus_ functions to use cpumask_* functions.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4464Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Remove unused and trivial PIC accesss functions, update nlm_pic_send_ipi()
and nlm_set_irt_to_cpu() to use similar logic, and use correct type for
reg in nlm_pic_disable_irt().
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4463Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Used the hardware thread id passed in while writing to IRT in
nlm_pic_init_irt()
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4465Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Add IRT to IRQ translation for the MMC and I2C IRQs.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3761/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The XLP USB controller appears as a device on the internal SoC PCIe
bus, the block has 2 EHCI blocks and 4 OHCI blocks. Change are to:

* Add files netlogic/xlp/usb-init.c and asm/netlogic/xlp-hal/usb.h
  to initialize the USB controller and define PCI fixups. The PCI
  fixups are to setup interrupts and DMA mask.
* Update include/asm/xlp-hal/{iomap.h,pic.h,xlp.h} to add interrupt
  mapping for EHCI/OHCI interrupts.
Signed-off-by: NGanesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3756/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Adds support for the XLP on-chip PCIe controller. On XLP, the
on-chip devices(including the 4 PCIe links) appear in the PCIe
configuration space of the XLP as PCI devices.

The changes are to initialize and register the PCIe controller,
enable hardware byte swap in the PCIe IO and MEM space, and to
enable PCIe interrupts.
Signed-off-by: NGanesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3760/
Patchwork: https://patchwork.linux-mips.org/patch/4104/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Changes to add support for the boot NOR flash on XLR boards and the
boot NAND/NOR flash drivers on the XLS boards.
Signed-off-by: NGanesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3758/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Remove NETLOGIC_ prefix from gpio register definitions, this will
bring it in-line with the other Netlogic headers.

Having NETLOGIC prefix here is misleading because these are XLR/XLS
specific register definitions.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3754/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Update for core intialization code.  Initialize status register
after receiving NMI for CPU wakeup. Add the low level L1D flush
code before enabling threads in core.

Also convert the ehb to _ehb so that it works under more GCC
versions.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3755/
Patchwork: https://patchwork.linux-mips.org/patch/4095/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Create a common NMI and reset handler in smpboot.S and use this for
both XLR and XLP.  In the earlier code, the woken up CPUs would
busy wait until released, switch this to wakeup by NMI.

The initial wakeup code or XLR and XLP are differ since they are
started from different bootloaders (XLP from u-boot and XLR from
netlogic bootloader). But in both platforms the woken up CPUs wait
and are released by sending an NMI.

Add support for starting XLR and XLP in 1/2/4 threads per core.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2970/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

- Update common files to support XLP.
- Add arch/mips/include/asm/netlogic/xlp-hal for register definitions
  and access macros
- Add arch/mips/netlogic/xlp/ for XLP specific files.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2967/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

- Move code that can be shared with XLP (irq.c, smp.c, time.c and
  xlr_console.c) to arch/mips/netlogic/common
- Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and
  io functions shared with XLP
- remove type 'nlm_reg_t *' and use uint64_t for mmio offsets
- Move XLR specific code in smp.c to xlr/wakeup.c
- Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c
- Provide API for pic functions called from common/irq.c
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2964/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add basic support for MSI.
Signed-off-by: NGanesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2730/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Adds pci/pci-xlr.c to support for XLR PCI/PCI-X interface and XLS PCIe
interface.
Update irq.c to ack PCI interrupts, use irq handler data to do the
PCI/PCIe bus ack.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2337/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

* include/asm/netlogic added with files common for all Netlogic processors
  (common with XLP which will be added later)
* include/asm/netlogic/xlr for XLR/XLS chip specific files
* netlogic/xlr for XLR/XLS platform files
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2334/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>