1. 07 11月, 2017 10 次提交
    • M
      PCI: Distribute available resources to hotplug-capable bridges · 1a576772
      Mika Westerberg 提交于
      The same problem that we have with bus space applies to other resources
      as well. Linux only allocates the minimal amount of resources so that
      the devices currently present barely fit there. This prevents extending
      the chain later on because the resource windows allocated for hotplug
      downstream ports are too small.
      
      Follow what we already did for bus number and assign all available extra
      resources to hotplug-capable bridges. This makes it possible to extend the
      hierarchy later.
      Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      1a576772
    • M
      PCI: Distribute available buses to hotplug-capable bridges · 1c02ea81
      Mika Westerberg 提交于
      System BIOS sometimes allocates extra bus space for hotplug-capable PCIe
      root/downstream ports. This space is needed if the device plugged to the
      port will have more hotplug-capable downstream ports. A good example of
      this is Thunderbolt. Each Thunderbolt device contains a PCIe switch and
      one or more hotplug-capable PCIe downstream ports where the daisy chain
      can be extended.
      
      Currently Linux only allocates minimal bus space to make sure all the
      enumerated devices barely fit there. The BIOS reserved extra space is
      not taken into consideration at all. Because of this we run out of bus
      space pretty quickly when more PCIe devices are attached to hotplug
      downstream ports in order to extend the chain.
      
      Modify the PCI core so we distribute the available BIOS allocated bus space
      equally between hotplug-capable bridges to make sure there is enough bus
      space for extending the hierarchy later on.
      
      Update kernel docs of the affected functions.
      Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      1c02ea81
    • M
      PCI: Do not allocate more buses than available in parent · a20c7f36
      Mika Westerberg 提交于
      One can ask more buses to be reserved for hotplug bridges by passing
      pci=hpbussize=N in the kernel command line.  If the parent bus does not
      have enough bus space available we incorrectly create child bus with the
      requested number of subordinate buses.
      
      In the example below hpbussize is set to one more than we have available
      buses in the root port:
      
        pci 0000:07:00.0: [8086:1578] type 01 class 0x060400
        pci 0000:07:00.0: scanning [bus 00-00] behind bridge, pass 0
        pci 0000:07:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
        pci 0000:07:00.0: scanning [bus 00-00] behind bridge, pass 1
        pci_bus 0000:08: busn_res: can not insert [bus 08-ff] under [bus 07-3f] (conflicts with (null) [bus 07-3f])
        pci_bus 0000:08: scanning bus
        ...
        pci_bus 0000:0a: bus scan returning with max=40
        pci_bus 0000:0a: busn_res: [bus 0a-ff] end is updated to 40
        pci_bus 0000:0a: [bus 0a-40] partially hidden behind bridge 0000:07 [bus 07-3f]
        pci_bus 0000:08: bus scan returning with max=40
        pci_bus 0000:08: busn_res: [bus 08-ff] end is updated to 40
      
      Instead of allowing this, limit the subordinate number to be less than or
      equal the maximum subordinate number allocated for the parent bus (if it
      has any).
      Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      [bhelgaas: remove irrelevant dmesg messages]
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      a20c7f36
    • M
      PCI: Open-code the two pass loop when scanning bridges · 4147c2fd
      Mika Westerberg 提交于
      The current scanning code is really hard to understand because it calls
      the same function in a loop where pass value is changed without any
      comments explaining it:
      
        for (pass = 0; pass < 2; pass++)
          for_each_pci_bridge(dev, bus)
            max = pci_scan_bridge(bus, dev, max, pass);
      
      Unfamiliar reader cannot tell easily what is the purpose of this loop
      without looking at internals of pci_scan_bridge().
      
      In order to make this bit easier to understand, open-code the loop in
      pci_scan_child_bus() and pci_hp_add_bridge() with added comments.
      
      No functional changes intended.
      Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      4147c2fd
    • M
      PCI: Move pci_hp_add_bridge() to drivers/pci/probe.c · 95e3ba97
      Mika Westerberg 提交于
      There is not much point of having a file with a single function in it.
      Instead we can just move pci_hp_add_bridge() to drivers/pci/probe.c and
      make it available always when PCI core is enabled.
      Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      [bhelgaas: convert printk to dev_err()]
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      95e3ba97
    • A
      PCI: Add for_each_pci_bridge() helper · 24a0c654
      Andy Shevchenko 提交于
      The following pattern is often used:
      
        list_for_each_entry(dev, &bus->devices, bus_list) {
          if (pci_is_bridge(dev)) {
            ...
          }
        }
      
      Add a for_each_pci_bridge() helper to make that code easier to write and
      read by reducing indentation level.  It also saves one or few lines of code
      in each occurrence.
      
      Convert PCI core parts here at the same time.
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      [bhelgaas: fold in http://lkml.kernel.org/r/20171013165352.25550-1-andriy.shevchenko@linux.intel.com]
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      24a0c654
    • K
      PCI: shpchp: Convert timers to use timer_setup() · 3691314a
      Kees Cook 提交于
      In preparation for unconditionally passing the struct timer_list pointer to
      all timer callbacks, switch to using the new timer_setup() and from_timer()
      to pass the timer pointer explicitly.
      Signed-off-by: NKees Cook <keescook@chromium.org>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
      Cc: Quentin Lambert <lambert.quentin@gmail.com>
      Cc: Aleksandr Bezzubikov <zuban32s@gmail.com>
      Cc: "Michael S. Tsirkin" <mst@redhat.com>
      Cc: Marcel Apfelbaum <marcel@redhat.com>
      3691314a
    • K
      PCI: cpqphp: Convert timers to use timer_setup() · 34d773f6
      Kees Cook 提交于
      In preparation for unconditionally passing the struct timer_list pointer to
      all timer callbacks, switch to using the new timer_setup() and from_timer()
      to pass the timer pointer explicitly.  This has the result of fixing
      pushbutton_helper_thread(), which was truncating the event pointer to 32
      bits.
      Signed-off-by: NKees Cook <keescook@chromium.org>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
      Cc: Quentin Lambert <lambert.quentin@gmail.com>
      Cc: Aleksandr Bezzubikov <zuban32s@gmail.com>
      Cc: "Michael S. Tsirkin" <mst@redhat.com>
      Cc: Marcel Apfelbaum <marcel@redhat.com>
      34d773f6
    • K
      PCI: pciehp: Convert timers to use timer_setup() · c4459a08
      Kees Cook 提交于
      In preparation for unconditionally passing the struct timer_list pointer to
      all timer callbacks, switch to using the new timer_setup() and from_timer()
      to pass the timer pointer explicitly. This fixes what appears to be a bug
      in passing the wrong pointer to the timer handler (address of ctrl pointer
      instead of ctrl pointer).
      Signed-off-by: NKees Cook <keescook@chromium.org>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
      Cc: Mayurkumar Patel <mayurkumar.patel@intel.com>
      Cc: Keith Busch <keith.busch@intel.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      c4459a08
    • M
      PCI: ibmphp: Use common error handling code in unconfigure_boot_device() · 05196e25
      Markus Elfring 提交于
      Combine two error paths that emit the same message and return the same
      error code.
      
      This issue was detected by using the Coccinelle software.
      Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
      [bhelgaas: changelog]
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      05196e25
  2. 26 9月, 2017 1 次提交
  3. 21 9月, 2017 1 次提交
  4. 15 9月, 2017 1 次提交
    • B
      Revert "PCI: Avoid race while enabling upstream bridges" · 0f50a49e
      Bjorn Helgaas 提交于
      This reverts commit 40f11adc.
      
      Jens found that iwlwifi firmware loading failed on a Lenovo X1 Carbon,
      gen4:
      
        iwlwifi 0000:04:00.0: Direct firmware load for iwlwifi-8000C-34.ucode failed with error -2
        iwlwifi 0000:04:00.0: Direct firmware load for iwlwifi-8000C-33.ucode failed with error -2
        iwlwifi 0000:04:00.0: Direct firmware load for iwlwifi-8000C-32.ucode failed with error -2
        iwlwifi 0000:04:00.0: loaded firmware version 31.532993.0 op_mode iwlmvm
        iwlwifi 0000:04:00.0: Detected Intel(R) Dual Band Wireless AC 8260, REV=0x208
        ...
        iwlwifi 0000:04:00.0: Failed to load firmware chunk!
        iwlwifi 0000:04:00.0: Could not load the [0] uCode section
        iwlwifi 0000:04:00.0: Failed to start INIT ucode: -110
        iwlwifi 0000:04:00.0: Failed to run INIT ucode: -110
      
      He bisected it to 40f11adc ("PCI: Avoid race while enabling upstream
      bridges").  Revert that commit to fix the regression.
      
      Link: http://lkml.kernel.org/r/4bcbcbc1-7c79-09f0-5071-bc2f53bf6574@kernel.dk
      Fixes: 40f11adc ("PCI: Avoid race while enabling upstream bridges")
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      CC: Srinath Mannam <srinath.mannam@broadcom.com>
      CC: Jens Axboe <axboe@kernel.dk>
      CC: Luca Coelho <luca@coelho.fi>
      CC: Johannes Berg <johannes@sipsolutions.net>
      CC: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
      0f50a49e
  5. 14 9月, 2017 1 次提交
  6. 07 9月, 2017 3 次提交
  7. 06 9月, 2017 11 次提交
  8. 02 9月, 2017 2 次提交
  9. 31 8月, 2017 2 次提交
  10. 30 8月, 2017 8 次提交