This reverts commit 6c7e660a.

The commit causes breakage on several older PXA machines.
Reported-by: NMike Dunn <mikedunn@newsguy.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since more driver names are added into platform id, do the same thing on
compatible names for DT mode.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Since PXA_GPIO_TO_IRQ() & MMP_GPIO_TO_IRQ() macro are depended on
arch code, move them from gpio driver to platform driver instead.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Avoid to use cpu_is_xxx() in pxa gpio driver. Use platform_device_id
to identify the difference.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

These functions have been introduced by commit 10a8c383 (irq: introduce
entry and exit functions for chained handlers) in asm/mach/irq.h. This
patch moves them to linux/irqchip/chained_irq.h so that generic irqchip
drivers do not rely on architecture specific header files.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Tested-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>

gpio & pinctrl driver are used together. The pinctrl driver is already
launched before gpio driver in Makefile. So set gpio driver to module
init level. Otherwise, the sequence will be inverted.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

CONFIG_HOTPLUG is going away as an option so __devinit is no longer
needed.
Signed-off-by: NBill Pemberton <wfp5p@virginia.edu>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

PXA95x isn't widely used. And it adds the effort on supporting
multiple platform. So remove it.

The assumption is that nobody will miss this support. If you are
reading this text because you actually require pxa95x support on
a new kernel, we can work out a way to revert this patch or add
support to the mmp platform.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Using for_each_set_bit() to simplify the code.

spatch with a semantic match is used to found this.
(http://coccinelle.lip6.fr/)
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Clk_prepare_enable and clk_disable_unprepare combine clk_prepare and
clk_enable, and clk_disable and clk_unprepare.  They make the code more
concise, and ensure that clk_unprepare is called when clk_enable fails.

A simplified version of the semantic patch that introduces calls to these
functions is as follows: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression e;
@@

- clk_prepare(e);
- clk_enable(e);
+ clk_prepare_enable(e);

@@
expression e;
@@

- clk_disable(e);
- clk_unprepare(e);
+ clk_disable_unprepare(e);
// </smpl>
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NChao Xie <xiechao.mail@gmail.com>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>

Simplify the code in gpio-pxa.c and make them based on irq_base.
When not probed from devicetree, initialize irq_base from
PXA_GPIO_TO_IRQ() or MMP_GPIO_TO_IRQ(), respectively, so the non-DT case
still works.

Only tested on PXA3xx.
Signed-off-by: NDaniel Mack <zonque@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>

Commit 72121572 ("GPIO: gpio-pxa: fix devicetree functions") added an
"xlate" function pointer to the irq_domain_ops, but this function is nor
declared or defined anywhere when CONFIG_OF is disabled, causing the
build error:

  drivers/gpio/gpio-pxa.c:532:11: error: 'irq_domain_xlate_twocell' undeclared here (not in a function)

Extending the DT-only code section to cover the irq_domain_ops and the
pxa_gpio_dt_ids solves this problem and makes it clearer which code is
actually used without DT.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Provide an of_xlate function for the PXA GPIO chips and make it work for
devicetree environments.

Successfully tested on a PXA3xx board.
Signed-off-by: NDaniel Mack <zonque@gmail.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Parse GPIO numbers from DTS file. Allocate interrupt according to
GPIO numbers.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

In 3.3, gpio wakeup setting was broken. The call
enable_irq_wake() didn't set up the PXA gpio registers
(PWER, ...) anymore.

Fix it at least for pxa27x. The driver doesn't seem to be
used in pxa25x (weird ...), and the fix doesn't extend to
pxa3xx and pxa95x (which don't have a gpio_set_wake()
available).
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>

In preparation to make mach/irqs.h optional and remove from asm/irq.h,
directly include mach/irq.h to get MMP_GPIO_TO_IRQ and PXA_GPIO_TO_IRQ.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Support clk in gpio driver. There's no gpio clock in PXA25x and PXA27x.
So use dummy clk instead. And move the gpio edge initialization into
gpio driver for arch-mmp.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>

Append code to clear gpio edge detect in gpio-pxa driver.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>

Remove most gpio macros and change gpio driver to platform driver.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>

Remove __raw_readl()/__raw_writel(). Use readl_relaxed()/writel_relaxed()
instead.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>

Use cpuid to recognize the gpio number and type. CPU_PXA26x is the
special case since we can't identify it by cpuid.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>

Avoid to define gpio_to_irq() and irq_to_gpio() for potential name
confliction since multiple architecture will be built together.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>

GPIO0 and GPIO1 are linked to unique interrupt line in PXA series,
others are linked to another interrupt line. All GPIO are linked to one
interrupt line in MMP series.

Since gpio driver is shared between PXA series and MMP series, define
GPIO0 and GPIO1 as chained interrupt chip. So we can move out gpio code
from irq.c to gpio-pxa.c.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>

The <mach/gpio.h> file is included from upper directories
and deal with generic GPIO and gpiolib stuff. Break out the
platform and driver specific defines and functions into its own
header file.

Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

As per example from the other ARM boards, push the PXA
GPIO driver down to the GPIO subsystem so it can be consolidated.
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Convert arch/arm includes of mach/gpio.h and asm/gpio.h to linux/gpio.h
before we start consolidating the individual platform implementations
of the gpio header files.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The PXA platform code has a static inline helper called
gpio_to_chip which clashes with the gpiolib namespace if we
try to expose the function with the same name from gpiolib,
and it's still confusing even if we don't do that. So rename
it to gpio_to_pxachip().
Reported-by: NH Hartley Sweeten <hartleys@visionengravers.com>
Cc: Eric Miao <eric.miao@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Replace sysdev classes and struct sys_device objects used for "core"
power management by the PXA platform code with struct syscore_ops
objects that are simpler.

This reduces the code size and the kernel memory footprint.  It also
is necessary for removing sysdevs entirely from the kernel in the
future.
Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
Acked-by: NGreg Kroah-Hartman <gregkh@suse.de>

Use irq_set_chip_and_handler() instead. Converted with coccinelle.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Convert to the new function names. Automated with coccinelle.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>

As slab is available early now, use kzalloc() rather than
alloc_bootmem_low() in pxa_init_gpio_chip().

This removes the following boot time warning:

<4>------------[ cut here ]------------
<4>WARNING: at mm/bootmem.c:535 alloc_arch_preferred_bootmem+0x2c/0x54()
<d>Modules linked in:
[<c0029430>] (unwind_backtrace+0x0/0xdc) from [<c0036f64>] (warn_slowpath_common+0x4c/0x80)
[<c0036f64>] (warn_slowpath_common+0x4c/0x80) from [<c000ede0>] (alloc_arch_preferred_bootmem+0x2c/0x54)
[<c000ede0>] (alloc_arch_preferred_bootmem+0x2c/0x54) from [<c000f2e4>] (___alloc_bootmem_nopanic+0x34/0xd0)
[<c000f2e4>] (___alloc_bootmem_nopanic+0x34/0xd0) from [<c000f6e4>] (___alloc_bootmem+0xc/0x34)
[<c000f6e4>] (___alloc_bootmem+0xc/0x34) from [<c000cb20>] (pxa_init_gpio+0x48/0x228)
[<c000cb20>] (pxa_init_gpio+0x48/0x228) from [<c0009794>] (init_IRQ+0x34/0x44)
[<c0009794>] (init_IRQ+0x34/0x44) from [<c00089d4>] (start_kernel+0x144/0x264)
[<c00089d4>] (start_kernel+0x144/0x264) from [<a0008034>] (0xa0008034)
<4>---[ end trace 1b75b31a2719ed1c ]---
Signed-off-by: NDaniel Mack <daniel@caiaq.de>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

pxa_gpio_irq_type() and pxa_unmask_muxed_gpio() will touch non-muxed GPIOs
(0 and 1 on PXA2xx/PXA3xx) bits in GRERx and GFERx, which is incorrect.
Actually, only those bits should get updated if the corresponding bits are
set in c->irq_mask as well. Fix this by updating only those relevant bits.
Reported-and-tested-by: NDaniel Ribeiro <drwyrm@gmail.com>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

1. add common GPIO handling code into [arch/arm/plat-pxa]

2. common code in <mach/gpio.h> moved into <plat/gpio.h>, new processors
   should implement its own <mach/gpio.h>, provide the following required
   definitions and '#include <plat/gpio.h>' in the end:

   - GPIO_REGS_VIRT for mapped virtual address of the GPIO registers'
     physical I/O memory

   - macros of GPLR(), GPSR(), GPDR() for constant optimization for
     functions gpio_{set,get}_value() (so that bit-bang code can still
     have tolerable performance)

   - NR_BUILTIN_GPIO for the number of onchip GPIO

   - definitions of __gpio_is_inverted() and __gpio_is_occupied(), they
     can be either macros or inlined functions
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Let's handle GPIOs by banks, each bank covers up to 32 GPIOs with one set
of registers, and each set of registers start from different offsets.

           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
 BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
 BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
 BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050

 BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
 BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
 BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150

 NOTE:
   BANK 3 is only available on PXA27x and later processors.
   BANK 4 and 5 are only available on PXA935

1. introduce GPIO_BANK(n) for the offset base of each bank

2. 'struct pxa_gpio_chip' is expanded to include IRQ edge and mask
   setings, and saved register values as well, and is dynamically
   allocated due to possible bank number ranging from 3 to 6

3. all accesses to GPIO registers are made through 'regbase' within
   'pxa_gpio_chip', and register offset

4. introduce several inline functions to simplify the code a bit

5. change IRQ demux handler to base on gpio chips
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Signed-off-by: NEric Miao <eric.miao@marvell.com>

This makes gpio.c fully independent of pxa-regs.h (except for the
virtual address of the registers).
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Looks like we have to live with pxa_gpio_mode() for a while, giving
its presence is actually making gpio.c not generic enough, let's
move it temporarily outside before it can be fully purged.
Signed-off-by: NEric Miao <eric.miao@marvell.com>

This is part of the work making gpio.c generic enough, the changes
include:

1. move IRQ handling of GPIO 0 and 1 outside (and back into irq.c)

2. pxa_init_gpio() accepts a range for muxed GPIO IRQs, and an IRQ
   number for the muxed GPIOs

3. __gpio_is_occupied() and __gpio_is_inverted() are made inline,
   and are moved into <mach/gpio.h> instead of generic gpio.c
Signed-off-by: NEric Miao <eric.miao@marvell.com>