This patch provides the skeleton of the HW perf event support. To enable
this feature, we can not choose the SMTC kernel; Oprofile should be
disabled; kernel performance events be selected. Then we can enable it in
Kernel type menu.

Oprofile for MIPS platforms initializes irq at arch init time. Currently
we do not change this logic to allow PMU reservation.

If a platform has EIC, we can use the irq base and perf counter irq offset
defines for the interrupt controller in specific init_hw_perf_events().

Based on this skeleton patch, the 3 different kinds of MIPS PMU, namely,
mipsxx/loongson2/rm9000, can be supported by adding corresponding lower
level C files at the bottom. The suggested names of these files are
perf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for
example, we can do this by adding "#include perf_event_mipsxx.c" at the
bottom of perf_event.c.

In addition, PMUs with 64bit counters are also considered in this patch.
Signed-off-by: NDeng-Cheng Zhu <dengcheng.zhu@gmail.com>
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Cc: ddaney@caviumnetworks.com
Cc: matt@console-pimps.org
Patchwork: https://patchwork.linux-mips.org/patch/1688/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Software events are required as part of the measurable stuff by the
Linux performance counter subsystem. Here is the list of events added by
this patch:
PERF_COUNT_SW_PAGE_FAULTS
PERF_COUNT_SW_PAGE_FAULTS_MIN
PERF_COUNT_SW_PAGE_FAULTS_MAJ
PERF_COUNT_SW_ALIGNMENT_FAULTS
PERF_COUNT_SW_EMULATION_FAULTS
Signed-off-by: NDeng-Cheng Zhu <dengcheng.zhu@gmail.com>
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Acked-by: NDavid Daney <ddaney@caviumnetworks.com>
Reviewed-by: NMatt Fleming <matt@console-pimps.org>
Patchwork: https://patchwork.linux-mips.org/patch/1686/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Perf-events is now using local_t helper functions internally. There is a
use of local_xchg(). On MIPS, this is defined to xchg_local() which is
missing in asm/system.h. This patch re-defines local_xchg() in asm/local.h
to atomic_long_xchg(). Then Perf-events can pass the build.
Signed-off-by: NDeng-Cheng Zhu <dengcheng.zhu@gmail.com>
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Cc: ddaney@caviumnetworks.com
Cc: matt@console-pimps.org
Patchwork: https://patchwork.linux-mips.org/patch/1687/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost
completely identical to AR7 except on a few points:
- a second bank of gpios is available
- vlynq0 on titan is vlynq1 on ar7
- different PHY addresses for cpmac0

This SoC can be found on commercial products like the Linksys WRTP54G

Original patch by Xin with improvments by Florian.
Signed-off-by: NXin Zhen <xlonestar2000@aim.com>
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/1563/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

---

In order to detect the Titan variant, we must initialize GPIOs earlier since
detection relies on some GPIO values to be set.
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/1562/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

---

Declare that OCTEON reference boards have both OHCI and EHCI.

Add platform devices for the corresponding hardware.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-usb@vger.kernel.org
To: dbrownell@users.sourceforge.net
Patchwork: http://patchwork.linux-mips.org/patch/1676/Acked-by: NGreg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The EHCI and OHCI blocks connection to the I/O bus is controlled by
these registers.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-usb@vger.kernel.org
To: dbrownell@users.sourceforge.net
Patchwork: http://patchwork.linux-mips.org/patch/1674/Acked-by: NGreg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

 create mode 100644 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h

The CN63XXP1 needs a couple of workarounds to ensure memory is not written
in unexpected ways.

All PREF with hints in the range 0-4,6-24 are replaced with PREF 28.  We
pass a flag to the assembler to cover compiler generated code, and patch
uasm for the dynamically generated code.

The write buffer threshold is reduced to 4.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1672/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The I2C and UARTS are clocked by the I/O clock, use its rate for these
devices.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1670/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Starting with cn63xx Octeon I/O blocks are clocked at a different rate
than the CPU.  Add a new function octeon_get_io_clock_rate() that
yields the I/O clock rate.

Also rearrange octeon_get_clock_rate() to get the value from the saved
sysinfo structure.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1671/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

We can run with any simulator clock rate.  Get rid of the code
overriding it to 6MHz.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1669/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The per-CPU clocks are synchronized from IPD_CLK_COUNT, on cn63XX it must
be scaled by the clock frequency ratio.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1667/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1666/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The OCTEON II ISA extends the original OCTEON ISA, so give it its own
__elf_platform string so optimized libraries can be selected in
userspace.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1665/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1664/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1662/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The CN63XX has a different L2 cache architecture.  Update the helper
functions to reflect this.

Some joining of split lines was also done to improve readability, as
well as reformatting of comments.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1663/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1661/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.

Join some lines back together.  This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1668/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

All Octeon chips can support more than 4GB of RAM.  Also due to how Octeon
PCI is setup, even some configurations with less than 4GB of RAM will have
portions that are not accessible from 32-bit devices.

Enable the swiotlb code to handle the cases where a device cannot directly
do DMA.  This is a complete rewrite of the Octeon DMA mapping code.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1639/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This allows platforms that are using the swiotlb to initialize it.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1638/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Use asm-generic/dma-mapping-common.h to handle all DMA mapping operations
and establish a default get_dma_ops() that forwards all operations to the
existing code.

Augment dev_archdata to carry a pointer to the struct dma_map_ops, allowing
DMA operations to be overridden on a per device basis.  Currently this is
never filled in, so the default dma_map_ops are used.  A follow-on patch
sets this for Octeon PCI devices.

Also initialize the dma_debug system as it is now used if it is configured.

Includes fixes by Kevin Cernekee <cernekee@gmail.com>.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1637/
Patchwork: http://patchwork.linux-mips.org/patch/1678/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Any function defined in a header file should be inline.  This helps us
avoid 'unused' compiler warnings when we include the files in more
places in subsequent patches.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1636/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Give us a nice place to allocate coherent DMA memory for 32-bit devices.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1635/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

On OCTEON, we reserve the last 256MB of 32-bit PCI address space, mapping
the RAM in this region at a high DMA address.  This makes memory in this
region unavailable for 32-bit DMA.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1634/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

DMA mapping may reduce the usable physical address range usable for
32-bit DMA.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1633/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This allows follow-on patches to dma mapping functions to work with
the octeon mgmt device..
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1632/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add stackoverflow detection to mips arch
Signed-off-by: NAdam Jiang <jiang.adam@gmail.com>
Cc: dmitri.vorobiev@movial.com
Cc: wuzhangjin@gmail.com
Cc: ddaney@caviumnetworks.com
Cc: peterz@infradead.org
Cc: fweisbec@gmail.com
Cc: tj@kernel.org
Cc: tglx@linutronix.de
Cc: mingo@elte.hu
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1559/
Patchwork: https://patchwork.linux-mips.org/patch/1651/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

arch/mips/Kconfig already sets GENERIC_HARDIRQS_NO__DO_IRQ unconditionally.
Remove the redundant select from the Loongson Kconfig.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

All callers were passing in 1 anyway.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

It was a nice optimization - on paper at least.  In practice it results in
branches that may exceed the maximum legal range for a branch.  We can
fight that problem with -ffunction-sections but -ffunction-sections again
is incompatible with -pg used by the function tracer.

By rewriting the loop around all simple LL/SC blocks to C we reduce the
amount of inline assembler and at the same time allow GCC to often fill
the branch delay slots with something sensible or whatever else clever
optimization it may have up in its sleeve.

With this optimization gone we also no longer need -ffunction-sections,
so drop it.

This optimization was originally introduced in 2.6.21, commit
5999eca25c1fd4b9b9aca7833b04d10fe4bc877d (linux-mips.org) rsp.
f65e4fa8 (kernel.org).

Original fix for the issues which caused me to pull this optimization by
Paul Gortmaker <paul.gortmaker@windriver.com>.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

For MMC1 Controller, card detect interrupt source is
twl6030 which is non-gpio. The card detect call back function provides
card present/absent status by reading MMC Control register present
on twl6030. This functionality was introduced in mfd tree on
track to kernel.org

Sync pandaboard to the same and make mmc work.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Madhusudhan Chikkature <madhu.cr@ti.com>
Cc: Adrian Hunter <adrian.hunter@nokia.com>
Cc: Samuel Ortiz <sameo@linux.intel.com>
Acked-by: NKishore Kadiyala <kishore.kadiyala@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Tested-by: NJarkko Nikula <jhnikula@gmail.com>
Acked-by: NMadhusudhan Chikkature <madhu.cr@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

In preparation for the addition of SPI support for the WM831x move the I2C
specific code into a separate file with a separate Kconfig option so the
I2C support can be excluded from the build.

Also update the 1133-EV1 PMIC module support for SMDK6410 to use the new
symbol.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

Adding card detect callback function and card detect configuration
function for MMC1 Controller on OMAP4.

Card detect configuration function does initial configuration of the
MMC Control & PullUp-PullDown registers of Phoenix.

For MMC1 Controller, card detect interrupt source is
twl6030 which is non-gpio. The card detect call back function provides
card present/absent status by reading MMC Control register present
on twl6030.

Since OMAP4 doesn't use any GPIO line as used in OMAP3 for card detect,
the suspend/resume initialization which was done in omap_hsmmc_gpio_init
previously is moved to the probe thus making it generic for both OMAP3 &
OMAP4.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Madhusudhan Chikkature <madhu.cr@ti.com>
Cc: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: NKishore Kadiyala <kishore.kadiyala@ti.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

On AP4EVB the card detect pin of the top SD/MMC slot is not directly
connected to the tmio/mmcif controller but to a GPIO pin, so polling
needs to be done for SDHI1 and MMCIF in order to support hotplug for
that slot. SHDI1 and MMCIF share that slot, and the used controller
is selected by a DIP switch.
This patch adds a helper function to check if a card is present in that
particular slot, registers this function with SDHI1 and MMCIF and enables
polling for SDHI1.
Signed-off-by: NArnd Hannemann <arnd@arndnet.de>
Tested-by: NYusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

Signed-off-by: NArnaud Lacombe <lacombar@gmail.com>
Signed-off-by: NMichal Marek <mmarek@suse.cz>

Commit 3e4d3af5 ("mm: stack based kmap_atomic()") overlooked the
fact that parisc uses kmap as a coherence mechanism, so even though we
have no highmem, we do need to supply our own versions of kmap (and
atomic).  This patch converts the parisc kmap to the form which is
needed to keep it compiling (it's a simple prototype and name change).
Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
Acked-by: NKyle McMartin <kyle@redhat.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This fixes up the __cpu_disable() path's IRQ migration for the
irq_data changes.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NZimny Lech <napohybelskurwysynom2010@gmail.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>