some platforms(BIOS or OS) may change ASPM configuration in
PCI Express Link Control Register directly and dynamically
regardless the device driver installation.
Checking if ASPM support during the driver init phase by reading
PCI Express Link Contrl Register doesn't make sense.
This refine/update assume L0S/L1 is defalut enabled as hw->ctrl_flags
inited. atl1c_set_aspm will set real configuration based on chip
capability to hardware register.
atl1c_disable_l0s_l1 and register definition of REG_PM_CTRL are
refined as well.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend
clear it after resume to enable pclk(PCIE clock) switch to
low frequency(25M) in some circumstances to save power.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

refine/update register REG_MASTER_CTRL definition according with
hardware spec.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

clear PCIE error status (error log is write-1-clear).
REG_PCIE_UC_SEVERITY is removed as it's a standard pcie register,
and using kernle API to access it.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

dmar_dly_cnt and dmaw_dly_cnt aren't used by hardware/driver any more.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

atl1c_configure_tx used a wrong value of MAX_TX_OFFLOAD_THRESH(9KB)
for TSO threshold.
the right value should be 7KB
Fast Ethernet controller doesn't support Jumbo frame.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

l1c_wait_until_idle is called for serval modules (TXQ/RXQ/TXMAC/RXMAC).
specific moudle have specific idle/busy status in reg REG_IDLE_STATUS.
the previous code return wrongly if all modules are in idle status,
regardless the 'stop' action is applied on individual module.
Refine the reg REG_IDLE_STATUS definition as well.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

threshold setting to control ASPM for diff chips are different.
currently, all gigabit-capability chips have limited-ASPM under
100M throughput.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

in some platforms, we found the max-read-request-size in Device Control
Register is set to 0 by (BIOS?) during bootup, this will cause the
performance(throughput) very bad.
Restore it to a min-value.
register definition of REG_DEVICE_CTRL is removed, using kernel API to
access it as it's a standard pcie register.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

using fixed TXQ config for l2cb and l1c regardless dmar_block
to make tx-DMA more stable.
register REG_TXQ_CTRL is refined as well.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

dmaw_block is never used in the driver, remove it.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

some fields of REG_DMA_CTRL(15C0) are wrong, replace with the newest one.
haredware uses fixed dma-write-block size, remove dmaw_block related code
in function atl1c_configure_dma.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

function atl1c_stop_mac uses wrong register of REG_TWSI_CTRL
to stop mac, replace it with REG_TXQ_CTRL.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

remove code related to rxq 1/2/3 since multi-q not support.
refine REG_RXQ_CTRL definition as well.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

TPD producer/consumer index is 16bit wide.
16bit read/write reduce the dependency of the 2 tpd rings (hi and lo)
rename reg(157C/1580) to keep name coninsistency.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

l1c & later chips don't support DMA for SMB.
CMB is removed from hardware.
reg(15C8) is used to trig interrupt by tpd threshold.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

VPD register is only used for L1(devid=PCI_DEVICE_ID_ATTANSIC_L1) to
access external NV-memory.
l1c & later chip doesn't use it any more.
PHY 0/1 registers occupy the last 2 slots of the dump table.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

remove HDS register as it doesn't exist in hardware.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

the multiple-RX-Q in hardware doesn't work,
all related register definition & code are removed.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

replace unavailable email of the author since he left with a mail-list.
update company info as well, Atheros was acquired by Qualcomm.
insert "100" to driver description since it support 100M controller.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

To prevent interrupts lost they should be dropped only if
they are scheduled via napi interfaces. In other case, there is
exists situation when napi handler process TX interrupt, stay in
RX processing and in that moment any other interrupt received.
Then before this patch TX bit in ISR will be cleaned, napi
schedule will not occur in case of currently processing event and
TX interrupt definitely will be lost.
Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

As the rx/tx handled inside napi handler, the cycle is
not needed now, because only the rx/tx need such kind of
processing.
Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Unfortunately it is not clear from code is usage of
IMR register possible or not. So, to prevent possible
side-effects of reading this register i prefer store
interrupts enable flag separately.
Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This function should be used later to set/remove proper
bits in imr to disable only rx ints.
Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Looks like direct writes to IMR register is not good idea,
because there are exist functions to make this work.
Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Make the tx ints processing same as rx ones via napi.
The idea got from e1000. The interrupt disabling is
still not fine grained.
Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This is first step, here there is no fine interrupt
disabling which cause TX/ERR interrupts stalling when
RX scheduled ints processed.
Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Remove rx from unlikely optimization in case of rx is very
likely thing for network card. This also reduce code a bit.
Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Problem:
There was two separate work_struct structures which share one
handler. Unfortunately getting atl1_adapter structure from
work_struct in case of DMA error was done from incorrect
offset which cause kernel panics.

Solution:
The useless work_struct for DMA error removed and
handler name changed to more generic one.
Signed-off-by: NTony Zelenoff <antonz@parallels.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Jay Cliburn <jcliburn@gmail.com>
Cc: Chris Snook <chris.snook@gmail.com>

Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Jay Cliburn <jcliburn@gmail.com>
Cc: Chris Snook <chris.snook@gmail.com>

No need for yet another #define for this.

Convert NODE_ADDRESS_SIZE use to ETH_ALEN and remove #define.
Use memcpy instead of a loop to copy an address.
Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

ATL1C_WORK_EVENT_RESET is zero so the original code here is a nop.  The
intent was to set the zero bit.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This driver attempts to use two TX rings but lacks proper support :

1) IRQ handler only takes care of TX completion on first TX ring
2) the stop/start logic uses the legacy functions (for non multiqueue
drivers)

This means all packets witk skb mark set to 1 are sent through high
queue but are never cleaned and queue eventualy fills and block the
device, triggering the infamous "NETDEV WATCHDOG" message.

Lets use a single TX ring to fix the problem, this driver is not a real
multiqueue one yet.

Minimal fix for stable kernels.
Reported-by: NThomas Meyer <thomas@m3y3r.de>
Tested-by: NThomas Meyer <thomas@m3y3r.de>
Signed-off-by: NEric Dumazet <eric.dumazet@gmail.com>
Cc: Jay Cliburn <jcliburn@gmail.com>
Cc: Chris Snook <chris.snook@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Set addr_assign_type correctly to NET_ADDR_RANDOM in case
a random MAC address was generated and assigned to the netdevice.

Fix error handling in atl1c_probe(). If atl1c_read_mac_addr()
couldn't get the hw mac address, and a random mac address get
set return the error code. Don't go to err_eeprom in
atl1c_probe(), use the generated MAC address in this case.

Reset the state to NET_ADDR_PERM as soon as the MAC get
changed via .ndo_set_mac_address.

v2: use bitops
Signed-off-by: NDanny Kukawka <danny.kukawka@bisect.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Replaced deprecating dev_alloc_skb with netdev_alloc_skb in drivers/net/ethernet
  - Removed extra skb->dev = dev after netdev_alloc_skb
Signed-off-by: NPradeep A Dalvi <netdev@pradeepdalvi.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

alloc_etherdev has a generic OOM/unable to alloc message.
Remove the duplicative messages after alloc_etherdev calls.
Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Per discussion with Ben Hutchings and David Miller, go through and
remove assignments of "N/A" to fw_version in various drivers'
.get_drvinfo routines.  While there clean-up some use of bare
constants and such.
Signed-off-by: NRick Jones <rick.jones2@hp.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>