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提交 e344b63e 编写于 作者: C Chris Zankel 提交者： Linus Torvalds
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[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 7 

The attached patches provides part 7 of an architecture implementation for the
Tensilica Xtensa CPU series.
Signed-off-by: NChris Zankel <chris@zankel.net>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
上级 9a8fd558
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include/asm-xtensa/xtensa/cacheasm.h 0 → 100644
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include/asm-xtensa/xtensa/cacheattrasm.h 0 → 100644
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#ifndef XTENSA_CACHEATTRASM_H
#define XTENSA_CACHEATTRASM_H
/*
* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
*
* include/asm-xtensa/xtensa/cacheattrasm.h -- assembler-specific
* CACHEATTR register related definitions that depend on CORE
* configuration.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002 Tensilica Inc.
*/
#include <xtensa/coreasm.h>
/*
* This header file defines assembler macros of the form:
* <x>cacheattr_<func>
* where:
* <x> is 'i', 'd' or absent for instruction, data
* or both caches; and
* <func> indicates the function of the macro.
*
* The following functions are defined:
*
* icacheattr_get
* Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
*
* dcacheattr_get
* Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
* (Note: for configs with a real CACHEATTR register, the
* above two macros are identical.)
*
* cacheattr_set
* Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
* Works even when changing one's own code's attributes.
*
* icacheattr_is_enabled label
* Branches to \label if I-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* dcacheattr_is_enabled label
* Branches to \label if D-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* cacheattr_is_enabled label
* Branches to \label if either I-cache or D-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* The following macros are only defined under certain conditions:
*
* icacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
* Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
*
* dcacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
* Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
*/
/*************************** GENERIC -- ALL CACHES ***************************/
/*
* _cacheattr_get
*
* (Internal macro.)
* Returns value of CACHEATTR register (or closest equivalent) in a2.
*
* Entry:
* (none)
* Exit:
* a2 value read from CACHEATTR
* a3-a5 clobbered (temporaries)
*/
.macro _cacheattr_get tlb
#if XCHAL_HAVE_CACHEATTR
rsr a2, CACHEATTR
#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
// DTLB and ITLB are independent, so there's no single
// cache attribute that can describe both. So for now
// just return the DTLB state.
movi a5, 0xE0000000
movi a2, 0
movi a3, 0
1: add a3, a3, a5 // next segment
r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
dsync // interlock???
slli a2, a2, 4
extui a4, a4, 0, 4 // extract CA
or a2, a2, a4
bnez a3, 1b
#else
// This macro isn't applicable to arbitrary MMU configurations.
// Just return zero.
movi a2, 0
#endif
.endm
.macro icacheattr_get
_cacheattr_get itlb
.endm
.macro dcacheattr_get
_cacheattr_get dtlb
.endm
#define XCHAL_CACHEATTR_ALL_BYPASS 0x22222222 /* default (powerup/reset) value of CACHEATTR, all BYPASS
mode (ie. disabled/bypassed caches) */
#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
#define XCHAL_FCA_ENAMASK 0x001A /* bitmap of fetch attributes that require enabled icache */
#define XCHAL_LCA_ENAMASK 0x0003 /* bitmap of load attributes that require enabled dcache */
#define XCHAL_SCA_ENAMASK 0x0003 /* bitmap of store attributes that require enabled dcache */
#define XCHAL_LSCA_ENAMASK (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK) /* l/s attrs requiring enabled dcache */
#define XCHAL_ALLCA_ENAMASK (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK) /* all attrs requiring enabled caches */
/*
* _cacheattr_is_enabled
*
* (Internal macro.)
* Branches to \label if CACHEATTR in a2 indicates an enabled
* cache, using mask in a3.
*
* Parameters:
* label where to branch to if cache is enabled
* Entry:
* a2 contains CACHEATTR value used to determine whether
* caches are enabled
* a3 16-bit constant where each bit correspond to
* one of the 16 possible CA values (in a CACHEATTR mask);
* CA values that indicate the cache is enabled
* have their corresponding bit set in this mask
* (eg. use XCHAL_xCA_ENAMASK , above)
* Exit:
* a2,a4,a5 clobbered
* SAR clobbered
*/
.macro _cacheattr_is_enabled label
movi a4, 8 // loop 8 times
.Lcaife\@:
extui a5, a2, 0, 4 // get CA nibble
ssr a5 // index into mask according to CA...
srl a5, a3 // ...and get CA's mask bit in a5 bit 0
bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
srli a2, a2, 4 // next nibble
addi a4, a4, -1
bnez a4, .Lcaife\@ // loop for each nibble
.endm
#else /* XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
.macro _cacheattr_is_enabled label
j \label // macro not applicable, assume caches always enabled
.endm
#endif /* XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
/*
* icacheattr_is_enabled
*
* Branches to \label if I-cache is enabled.
*
* Parameters:
* label where to branch to if icache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro icacheattr_is_enabled label
#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
icacheattr_get
movi a3, XCHAL_FCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* dcacheattr_is_enabled
*
* Branches to \label if D-cache is enabled.
*
* Parameters:
* label where to branch to if dcache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro dcacheattr_is_enabled label
#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
dcacheattr_get
movi a3, XCHAL_LSCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* cacheattr_is_enabled
*
* Branches to \label if either I-cache or D-cache is enabled.
*
* Parameters:
* label where to branch to if a cache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro cacheattr_is_enabled label
#if XCHAL_HAVE_CACHEATTR
rsr a2, CACHEATTR
movi a3, XCHAL_ALLCA_ENAMASK
#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
icacheattr_get
movi a3, XCHAL_FCA_ENAMASK
_cacheattr_is_enabled \label
dcacheattr_get
movi a3, XCHAL_LSCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* The ISA does not have a defined way to change the
* instruction cache attributes of the running code,
* ie. of the memory area that encloses the current PC.
* However, each micro-architecture (or class of
* configurations within a micro-architecture)
* provides a way to deal with this issue.
*
* Here are a few macros used to implement the relevant
* approach taken.
*/
#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
/*
* icacheattr_set
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro icacheattr_set
movi a5, 0xE0000000 // mask of upper 3 bits
movi a6, 3f // PC where ITLB is set
movi a3, 0 // start at region 0 (0 .. 7)
and a6, a6, a5 // upper 3 bits of local PC area
mov a7, a2 // copy a2 so it doesn't get clobbered
j 3f
# if XCHAL_HAVE_XLT_CACHEATTR
// Can do translations, use generic method:
1: sub a6, a3, a5 // address of some other segment
ritlb1 a8, a6 // save its PPN+CA
dsync // interlock??
witlb a4, a6 // make it translate to this code area
movi a6, 5f // where to jump into it
isync
sub a6, a6, a5 // adjust jump address within that other segment
jx a6
// Note that in the following code snippet, which runs at a different virtual
// address than it is assembled for, we avoid using literals (eg. via movi/l32r)
// just in case literals end up in a different 512 MB segment, and we avoid
// instructions that rely on the current PC being what is expected.
//
.align 4
_j 6f // this is at label '5' minus 4 bytes
.align 4
5: witlb a4, a3 // we're in other segment, now can write previous segment's CA
isync
add a6, a6, a5 // back to previous segment
addi a6, a6, -4 // next jump label
jx a6
6: sub a6, a3, a5 // address of some other segment
witlb a8, a6 // restore PPN+CA of other segment
mov a6, a3 // restore a6
isync
# else /* XCHAL_HAVE_XLT_CACHEATTR */
// Use micro-architecture specific method.
// The following 4-instruction sequence is aligned such that
// it all fits within a single I-cache line. Sixteen byte
// alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
// actually causes problems because that can be greater than
// the alignment of the reset vector, where this macro is often
// invoked, which would cause the linker to align the reset
// vector code away from the reset vector!!).
.align 16 /*XCHAL_ICACHE_LINESIZE*/
1: _witlb a4, a3 // write wired PTE (CA, no PPN) of 512MB segment to ITLB
_isync
nop
nop
# endif /* XCHAL_HAVE_XLT_CACHEATTR */
beq a3, a5, 4f // done?
// Note that in the WITLB loop, we don't do any load/stores
// (may not be an issue here, but it is important in the DTLB case).
2: srli a7, a7, 4 // next CA
sub a3, a3, a5 // next segment (add 0x20000000)
3:
# if XCHAL_HAVE_XLT_CACHEATTR /* if have translation, preserve it */
ritlb1 a8, a3 // get current PPN+CA of segment
dsync // interlock???
extui a4, a7, 0, 4 // extract CA to set
srli a8, a8, 4 // clear CA but keep PPN ...
slli a8, a8, 4 // ...
add a4, a4, a8 // combine new CA with PPN to preserve
# else
extui a4, a7, 0, 4 // extract CA
# endif
beq a3, a6, 1b // current PC's region? if so, do it in a safe way
witlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
bne a3, a5, 2b
isync // make sure all ifetch changes take effect
4:
.endm // icacheattr_set
/*
* dcacheattr_set
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro dcacheattr_set
movi a5, 0xE0000000 // mask of upper 3 bits
movi a3, 0 // start at region 0 (0 .. 7)
mov a7, a2 // copy a2 so it doesn't get clobbered
j 3f
// Note that in the WDTLB loop, we don't do any load/stores
// (including implicit l32r via movi) because it isn't safe.
2: srli a7, a7, 4 // next CA
sub a3, a3, a5 // next segment (add 0x20000000)
3:
# if XCHAL_HAVE_XLT_CACHEATTR /* if have translation, preserve it */
rdtlb1 a8, a3 // get current PPN+CA of segment
dsync // interlock???
extui a4, a7, 0, 4 // extract CA to set
srli a8, a8, 4 // clear CA but keep PPN ...
slli a8, a8, 4 // ...
add a4, a4, a8 // combine new CA with PPN to preserve
# else
extui a4, a7, 0, 4 // extract CA to set
# endif
wdtlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
bne a3, a5, 2b
dsync // make sure all data path changes take effect
.endm // dcacheattr_set
#endif /* XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR */
/*
* cacheattr_set
*
* Macro that sets the current CACHEATTR safely
* (both i and d) according to the current contents of a2.
* It works even when changing the cache attributes of
* the currently running code.
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro cacheattr_set
#if XCHAL_HAVE_CACHEATTR
# if XCHAL_ICACHE_LINESIZE < 4
// No i-cache, so can always safely write to CACHEATTR:
wsr a2, CACHEATTR
# else
// The Athens micro-architecture, when using the old
// exception architecture option (ie. with the CACHEATTR register)
// allows changing the cache attributes of the running code
// using the following exact sequence aligned to be within
// an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE
// alignment actually causes problems because that can be greater
// than the alignment of the reset vector, where this macro is often
// invoked, which would cause the linker to align the reset
// vector code away from the reset vector!!).
j 1f
.align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line
1: _wsr a2, CACHEATTR
_isync
nop
nop
# endif
#elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
// DTLB and ITLB are independent, but to keep semantics
// of this macro we simply write to both.
icacheattr_set
dcacheattr_set
#else
// This macro isn't applicable to arbitrary MMU configurations.
// Do nothing in this case.
#endif
.endm
#endif /*XTENSA_CACHEATTRASM_H*/
include/asm-xtensa/xtensa/config-linux_be/core.h 0 → 100644
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此差异已折叠。
include/asm-xtensa/xtensa/config-linux_be/defs.h 0 → 100644
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/* Definitions for Xtensa instructions, types, and protos. */
/*
* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2.1 of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Further, this software is distributed without any warranty that it is
* free of the rightful claim of any third person regarding infringement
* or the like. Any license provided herein, whether implied or
* otherwise, applies only to this software file. Patent licenses, if
* any, provided herein do not apply to combinations of this program with
* other software, or any other product whatsoever.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
* USA.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#if defined(__GNUC__) && !defined(__XCC__)
#define L8UI_ASM(arr, ars, imm) { \
__asm__ volatile("l8ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L8UI(ars, imm) \
({ \
unsigned char _arr; \
const unsigned char *_ars = ars; \
L8UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16UI_ASM(arr, ars, imm) { \
__asm__ volatile("l16ui %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16UI(ars, imm) \
({ \
unsigned short _arr; \
const unsigned short *_ars = ars; \
L16UI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L16SI_ASM(arr, ars, imm) {\
__asm__ volatile("l16si %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L16SI(ars, imm) \
({ \
signed short _arr; \
const signed short *_ars = ars; \
L16SI_ASM(_arr, _ars, imm); \
_arr; \
})
#define L32I_ASM(arr, ars, imm) { \
__asm__ volatile("l32i %0, %1, %2" : "=a" (arr) : "a" (ars) , "i" (imm)); \
}
#define XT_L32I(ars, imm) \
({ \
unsigned _arr; \
const unsigned *_ars = ars; \
L32I_ASM(_arr, _ars, imm); \
_arr; \
})
#define S8I_ASM(arr, ars, imm) {\
__asm__ volatile("s8i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S8I(arr, ars, imm) \
({ \
signed char _arr = arr; \
const signed char *_ars = ars; \
S8I_ASM(_arr, _ars, imm); \
})
#define S16I_ASM(arr, ars, imm) {\
__asm__ volatile("s16i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S16I(arr, ars, imm) \
({ \
signed short _arr = arr; \
const signed short *_ars = ars; \
S16I_ASM(_arr, _ars, imm); \
})
#define S32I_ASM(arr, ars, imm) { \
__asm__ volatile("s32i %0, %1, %2" : : "a" (arr), "a" (ars) , "i" (imm) : "memory" ); \
}
#define XT_S32I(arr, ars, imm) \
({ \
signed int _arr = arr; \
const signed int *_ars = ars; \
S32I_ASM(_arr, _ars, imm); \
})
#define ADDI_ASM(art, ars, imm) {\
__asm__ ("addi %0, %1, %2" : "=a" (art) : "a" (ars), "i" (imm)); \
}
#define XT_ADDI(ars, imm) \
({ \
unsigned _art; \
unsigned _ars = ars; \
ADDI_ASM(_art, _ars, imm); \
_art; \
})
#define ABS_ASM(arr, art) {\
__asm__ ("abs %0, %1" : "=a" (arr) : "a" (art)); \
}
#define XT_ABS(art) \
({ \
unsigned _arr; \
signed _art = art; \
ABS_ASM(_arr, _art); \
_arr; \
})
/* Note: In the following macros that reference SAR, the magic "state"
register is used to capture the dependency on SAR. This is because
SAR is a 5-bit register and thus there are no C types that can be
used to represent it. It doesn't appear that the SAR register is
even relevant to GCC, but it is marked as "clobbered" just in
case. */
#define SRC_ASM(arr, ars, art) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("src %0, %1, %2" \
: "=a" (arr) : "a" (ars), "a" (art), "t" (_xt_sar)); \
}
#define XT_SRC(ars, art) \
({ \
unsigned _arr; \
unsigned _ars = ars; \
unsigned _art = art; \
SRC_ASM(_arr, _ars, _art); \
_arr; \
})
#define SSR_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssr %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSR(ars) \
({ \
unsigned _ars = ars; \
SSR_ASM(_ars); \
})
#define SSL_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssl %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSL(ars) \
({ \
unsigned _ars = ars; \
SSL_ASM(_ars); \
})
#define SSA8B_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8b %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8B(ars) \
({ \
unsigned _ars = ars; \
SSA8B_ASM(_ars); \
})
#define SSA8L_ASM(ars) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssa8l %1" : "=t" (_xt_sar) : "a" (ars) : "sar"); \
}
#define XT_SSA8L(ars) \
({ \
unsigned _ars = ars; \
SSA8L_ASM(_ars); \
})
#define SSAI_ASM(imm) {\
register int _xt_sar __asm__ ("state"); \
__asm__ ("ssai %1" : "=t" (_xt_sar) : "i" (imm) : "sar"); \
}
#define XT_SSAI(imm) \
({ \
SSAI_ASM(imm); \
})
#endif /* __GNUC__ && !__XCC__ */
#ifdef __XCC__
/* Core load/store instructions */
extern unsigned char _TIE_L8UI(const unsigned char * ars, immediate imm);
extern unsigned short _TIE_L16UI(const unsigned short * ars, immediate imm);
extern signed short _TIE_L16SI(const signed short * ars, immediate imm);
extern unsigned _TIE_L32I(const unsigned * ars, immediate imm);
extern void _TIE_S8I(unsigned char arr, unsigned char * ars, immediate imm);
extern void _TIE_S16I(unsigned short arr, unsigned short * ars, immediate imm);
extern void _TIE_S32I(unsigned arr, unsigned * ars, immediate imm);
#define XT_L8UI _TIE_L8UI
#define XT_L16UI _TIE_L16UI
#define XT_L16SI _TIE_L16SI
#define XT_L32I _TIE_L32I
#define XT_S8I _TIE_S8I
#define XT_S16I _TIE_S16I
#define XT_S32I _TIE_S32I
/* Add-immediate instruction */
extern unsigned _TIE_ADDI(unsigned ars, immediate imm);
#define XT_ADDI _TIE_ADDI
/* Absolute value instruction */
extern unsigned _TIE_ABS(int art);
#define XT_ABS _TIE_ABS
/* funnel shift instructions */
extern unsigned _TIE_SRC(unsigned ars, unsigned art);
#define XT_SRC _TIE_SRC
extern void _TIE_SSR(unsigned ars);
#define XT_SSR _TIE_SSR
extern void _TIE_SSL(unsigned ars);
#define XT_SSL _TIE_SSL
extern void _TIE_SSA8B(unsigned ars);
#define XT_SSA8B _TIE_SSA8B
extern void _TIE_SSA8L(unsigned ars);
#define XT_SSA8L _TIE_SSA8L
extern void _TIE_SSAI(immediate imm);
#define XT_SSAI _TIE_SSAI
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */
include/asm-xtensa/xtensa/config-linux_be/specreg.h 0 → 100644
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/*
* Xtensa Special Register symbolic names
*/
/* $Id: specreg.h,v 1.2 2003/03/07 19:15:18 joetaylor Exp $ */
/*
* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2.1 of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Further, this software is distributed without any warranty that it is
* free of the rightful claim of any third person regarding infringement
* or the like. Any license provided herein, whether implied or
* otherwise, applies only to this software file. Patent licenses, if
* any, provided herein do not apply to combinations of this program with
* other software, or any other product whatsoever.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
* USA.
*/
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
#include <xtensa/corebits.h>
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define DDR 104
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define INTERRUPT 226
#define INTENABLE 228
#define PS 230
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
/* Special cases (bases of special register series): */
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
/* Special names for read-only and write-only interrupt registers: */
#define INTREAD 226
#define INTSET 226
#define INTCLEAR 227
#endif /* XTENSA_SPECREG_H */
include/asm-xtensa/xtensa/config-linux_be/system.h 0 → 100644
浏览文件 @ e344b63e
/*
* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
*
* NOTE: The location and contents of this file are highly subject to change.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* The HAL itself has historically included this file in some instances,
* but this is not appropriate either, because the HAL is meant to be
* core-specific but system independent.
*/
/*
* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2.1 of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Further, this software is distributed without any warranty that it is
* free of the rightful claim of any third person regarding infringement
* or the like. Any license provided herein, whether implied or
* otherwise, applies only to this software file. Patent licenses, if
* any, provided herein do not apply to combinations of this program with
* other software, or any other product whatsoever.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
* USA.
*/
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H
/*#include <xtensa/hal.h>*/
/*----------------------------------------------------------------------
DEVICE ADDRESSES
----------------------------------------------------------------------*/
/*
* Strange place to find these, but the configuration GUI
* allows moving these around to account for various core
* configurations. Specific boards (and their BSP software)
* will have specific meanings for these components.
*/
/* I/O Block areas: */
#define XSHAL_IOBLOCK_CACHED_VADDR 0xE0000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0xF0000000
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
/* System ROM: */
#define XSHAL_ROM_VADDR 0xEE000000
#define XSHAL_ROM_PADDR 0xFE000000
#define XSHAL_ROM_SIZE 0x00400000
/* Largest available area (free of vectors): */
#define XSHAL_ROM_AVAIL_VADDR 0xEE00052C
#define XSHAL_ROM_AVAIL_VSIZE 0x003FFAD4
/* System RAM: */
#define XSHAL_RAM_VADDR 0xD0000000
#define XSHAL_RAM_PADDR 0x00000000
#define XSHAL_RAM_VSIZE 0x08000000
#define XSHAL_RAM_PSIZE 0x10000000
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
/* Largest available area (free of vectors): */
#define XSHAL_RAM_AVAIL_VADDR 0xD0000370
#define XSHAL_RAM_AVAIL_VSIZE 0x07FFFC90
/*
* Shadow system RAM (same device as system RAM, at different address).
* (Emulation boards need this for the SONIC Ethernet driver
* when data caches are configured for writeback mode.)
* NOTE: on full MMU configs, this points to the BYPASS virtual address
* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
* addresses are viewed through the BYPASS static map rather than
* the CACHED static map.
*/
#define XSHAL_RAM_BYPASS_VADDR 0xD8000000
#define XSHAL_RAM_BYPASS_PADDR 0x00000000
#define XSHAL_RAM_BYPASS_PSIZE 0x08000000
/* Alternate system RAM (different device than system RAM): */
#define XSHAL_ALTRAM_VADDR 0xCEE00000
#define XSHAL_ALTRAM_PADDR 0xC0000000
#define XSHAL_ALTRAM_SIZE 0x00200000
/*----------------------------------------------------------------------
* DEVICE-ADDRESS DEPENDENT...
*
* Values written to CACHEATTR special register (or its equivalent)
* to enable and disable caches in various modes.
*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------
BACKWARD COMPATIBILITY ...
----------------------------------------------------------------------*/
/*
* NOTE: the following two macros are DEPRECATED. Use the latter
* board-specific macros instead, which are specially tuned for the
* particular target environments' memory maps.
*/
#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
/*----------------------------------------------------------------------
ISS (Instruction Set Simulator) SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_ISS_CACHEATTR_WRITEBACK 0x1122222F /* enable caches in write-back mode */
#define XSHAL_ISS_CACHEATTR_WRITEALLOC 0x1122222F /* enable caches in write-allocate mode */
#define XSHAL_ISS_CACHEATTR_WRITETHRU 0x1122222F /* enable caches in write-through mode */
#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
/* For Coware only: */
#define XSHAL_COWARE_CACHEATTR_WRITEBACK 0x11222222 /* enable caches in write-back mode */
#define XSHAL_COWARE_CACHEATTR_WRITEALLOC 0x11222222 /* enable caches in write-allocate mode */
#define XSHAL_COWARE_CACHEATTR_WRITETHRU 0x11222222 /* enable caches in write-through mode */
#define XSHAL_COWARE_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
#define XSHAL_COWARE_CACHEATTR_DEFAULT XSHAL_COWARE_CACHEATTR_WRITEBACK /* default setting to enable caches */
/* For BFM and other purposes: */
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x11222222 /* enable caches without any invalid regions */
#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting for caches without any invalid regions */
#define XSHAL_ISS_PIPE_REGIONS 0
#define XSHAL_ISS_SDRAM_REGIONS 0
/*----------------------------------------------------------------------
XT2000 BOARD SPECIFIC ...
----------------------------------------------------------------------*/
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x22FFFFFF /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x22FFFFFF /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x22FFFFFF /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0x22FFFFFF /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_XT2000_PIPE_REGIONS 0x00001000 /* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000005 /* BusInt SDRAM regions */
/*----------------------------------------------------------------------
VECTOR SIZES
----------------------------------------------------------------------*/
/*
* Sizes allocated to vectors by the system (memory map) configuration.
* These sizes are constrained by core configuration (eg. one vector's
* code cannot overflow into another vector) but are dependent on the
* system or board (or LSP) memory map configuration.
*
* Whether or not each vector happens to be in a system ROM is also
* a system configuration matter, sometimes useful, included here also:
*/
#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
#define XSHAL_RESET_VECTOR_ISROM 1
#define XSHAL_USER_VECTOR_SIZE 0x0000001C
#define XSHAL_USER_VECTOR_ISROM 0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C
#define XSHAL_KERNEL_VECTOR_ISROM 0
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x000000E0
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000180
#define XSHAL_WINDOW_VECTORS_ISROM 0
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000000C
#define XSHAL_INTLEVEL4_VECTOR_ISROM 1
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM
#endif /*XTENSA_CONFIG_SYSTEM_H*/
include/asm-xtensa/xtensa/config-linux_be/tie.h 0 → 100644
浏览文件 @ e344b63e
/*
* xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
*
* This header file is sometimes referred to as the "compile-time HAL" or CHAL.
* It was generated for a specific Xtensa processor configuration,
* and furthermore for a specific set of TIE source files that extend
* basic core functionality.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL source itself to include this file.
*/
/*
* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2.1 of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Further, this software is distributed without any warranty that it is
* free of the rightful claim of any third person regarding infringement
* or the like. Any license provided herein, whether implied or
* otherwise, applies only to this software file. Patent licenses, if
* any, provided herein do not apply to combinations of this program with
* other software, or any other product whatsoever.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
* USA.
*/
#ifndef XTENSA_CONFIG_TIE_H
#define XTENSA_CONFIG_TIE_H
#include <xtensa/hal.h>
/*----------------------------------------------------------------------
GENERAL
----------------------------------------------------------------------*/
/*
* Separators for macros that expand into arrays.
* These can be predefined by files that #include this one,
* when different separators are required.
*/
/* Element separator for macros that expand into 1-dimensional arrays: */
#ifndef XCHAL_SEP
#define XCHAL_SEP ,
#endif
/* Array separator for macros that expand into 2-dimensional arrays: */
#ifndef XCHAL_SEP2
#define XCHAL_SEP2 },{
#endif
/*----------------------------------------------------------------------
COPROCESSORS and EXTRA STATE
----------------------------------------------------------------------*/
#define XCHAL_CP_NUM 0 /* number of coprocessors */
#define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
/* Space for coprocessors' state save areas: */
#define XCHAL_CP0_SA_SIZE 0
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP7_SA_SIZE 0
/* Minimum required alignments of CP state save areas: */
#define XCHAL_CP0_SA_ALIGN 1
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_ALIGN 1
/* Indexing macros: */
#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
/* Space for "extra" state (user special registers and non-cp TIE) save area: */
#define XCHAL_EXTRA_SA_SIZE 0
#define XCHAL_EXTRA_SA_ALIGN 1
/* Total save area size (extra + all coprocessors) */
/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
/* but included for Tor2 beta; doesn't account for alignment!): */
#define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
/* Combined required alignment for all CP and EXTRA state save areas */
/* (does not include required alignment for any base config registers): */
#define XCHAL_CPEXTRA_SA_ALIGN 1
/* ... */
#ifdef _ASMLANGUAGE
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
#include <xtensa/config/specreg.h>
/********************
* Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
*/
/* (none) */
/********************
* Macros to create functions that save and restore all EXTRA (non-coprocessor) state
* (does not include zero-overhead loop registers and non-optional registers).
*/
/*
* Macro that expands to the body of a function that
* stores the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area in which to save extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_store_funcbody
.endm
/*
* Macro that expands to the body of a function that
* loads the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area from which to restore extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_load_funcbody
.endm
/********************
* Macros to save and restore the state of each TIE coprocessor.
*/
/********************
* Macros to create functions that save and restore the state of *any* TIE coprocessor.
*/
/*
* Macro that expands to the body of a function
* that stores the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area in which to save cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_store_funcbody
.endm
/*
* Macro that expands to the body of a function
* that loads the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area from which to restore cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_load_funcbody
.endm
#endif /*_ASMLANGUAGE*/
/*
* Contents of save areas in terms of libdb register numbers.
* NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
* it is up to the user of this header file to define these macros
* usefully before each expansion of the CONTENTS_LIBDB macros.
* (Fields rsv[123] are reserved for future additions; they are currently
* set to zero but may be set to some useful values in the future.)
*
* CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
*/
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#if 0 /* is there something equivalent for user TIE? */
#define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
(CoreID) set in the Xtensa Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
#define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
#define XTHAL_HW_REL_T1050_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
#endif /*0*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#if 0 /* these probably don't belong here, but are related to or implemented using TIE */
#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
/* Misc instructions: */
#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
#endif /*0*/
#endif /*XTENSA_CONFIG_TIE_H*/
include/asm-xtensa/xtensa/coreasm.h 0 → 100644
浏览文件 @ e344b63e
#ifndef XTENSA_COREASM_H
#define XTENSA_COREASM_H
/*
* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
*
* include/asm-xtensa/xtensa/coreasm.h -- assembler-specific
* definitions that depend on CORE configuration.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL itself to include this
* file.
*
* This file must NOT include xtensa/config/system.h. Any assembler
* header file that depends on system information should likely go in
* a new systemasm.h (or sysasm.h) header file.
*
* NOTE: macro beqi32 is NOT configuration-dependent, and is placed
* here til we will have configuration-independent header file.
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of
* this archive for more details.
*
* Copyright (C) 2002 Tensilica Inc.
*/
#include <xtensa/config/core.h>
#include <xtensa/config/specreg.h>
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
/*----------------------------------------------------------------------
* find_ms_setbit
*
* This macro finds the most significant bit that is set in <as>
* and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
* The index counts starting at zero for the lsbit, so the return
* value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
*
* Parameters:
* <ad> destination address register (any register)
* <as> source address register
* <at> temporary address register (must be different than <as>)
* <base> constant value added to result (usually 0 or 1)
* On entry:
* <ad> = undefined if different than <as>
* <as> = value whose most significant set bit is to be found
* <at> = undefined
* no other registers are used by this macro.
* On exit:
* <ad> = <base> + index of msbit set in original <as>,
* = <base> - 1 if original <as> was zero.
* <as> clobbered (if not <ad>)
* <at> clobbered (if not <ad>)
* Example:
* find_ms_setbit a0, a4, a0, 0 -- return in a0 index of msbit set in a4
*/
.macro find_ms_setbit ad, as, at, base
#if XCHAL_HAVE_NSA
movi \at, 31+\base
nsau \as, \as // get index of \as, numbered from msbit (32 if absent)
sub \ad, \at, \as // get numbering from lsbit (0..31, -1 if absent)
#else /* XCHAL_HAVE_NSA */
movi \at, \base // start with result of 0 (point to lsbit of 32)
beqz \as, 2f // special case for zero argument: return -1
bltui \as, 0x10000, 1f // is it one of the 16 lsbits? (if so, check lower 16 bits)
addi \at, \at, 16 // no, increment result to upper 16 bits (of 32)
//srli \as, \as, 16 // check upper half (shift right 16 bits)
extui \as, \as, 16, 16 // check upper half (shift right 16 bits)
1: bltui \as, 0x100, 1f // is it one of the 8 lsbits? (if so, check lower 8 bits)
addi \at, \at, 8 // no, increment result to upper 8 bits (of 16)
srli \as, \as, 8 // shift right to check upper 8 bits
1: bltui \as, 0x10, 1f // is it one of the 4 lsbits? (if so, check lower 4 bits)
addi \at, \at, 4 // no, increment result to upper 4 bits (of 8)
srli \as, \as, 4 // shift right 4 bits to check upper half
1: bltui \as, 0x4, 1f // is it one of the 2 lsbits? (if so, check lower 2 bits)
addi \at, \at, 2 // no, increment result to upper 2 bits (of 4)
srli \as, \as, 2 // shift right 2 bits to check upper half
1: bltui \as, 0x2, 1f // is it the lsbit?
addi \at, \at, 2 // no, increment result to upper bit (of 2)
2: addi \at, \at, -1 // (from just above: add 1; from beqz: return -1)
//srli \as, \as, 1
1: // done! \at contains index of msbit set (or -1 if none set)
.if 0x\ad - 0x\at // destination different than \at ? (works because regs are a0-a15)
mov \ad, \at // then move result to \ad
.endif
#endif /* XCHAL_HAVE_NSA */
.endm // find_ms_setbit
/*----------------------------------------------------------------------
* find_ls_setbit
*
* This macro finds the least significant bit that is set in <as>,
* and return its index in <ad>.
* Usage is the same as for the find_ms_setbit macro.
* Example:
* find_ls_setbit a0, a4, a0, 0 -- return in a0 index of lsbit set in a4
*/
.macro find_ls_setbit ad, as, at, base
neg \at, \as // keep only the least-significant bit that is set...
and \as, \at, \as // ... in \as
find_ms_setbit \ad, \as, \at, \base
.endm // find_ls_setbit
/*----------------------------------------------------------------------
* find_ls_one
*
* Same as find_ls_setbit with base zero.
* Source (as) and destination (ad) registers must be different.
* Provided for backward compatibility.
*/
.macro find_ls_one ad, as
find_ls_setbit \ad, \as, \ad, 0
.endm // find_ls_one
/*----------------------------------------------------------------------
* floop, floopnez, floopgtz, floopend
*
* These macros are used for fast inner loops that
* work whether or not the Loops options is configured.
* If the Loops option is configured, they simply use
* the zero-overhead LOOP instructions; otherwise
* they use explicit decrement and branch instructions.
*
* They are used in pairs, with floop, floopnez or floopgtz
* at the beginning of the loop, and floopend at the end.
*
* Each pair of loop macro calls must be given the loop count
* address register and a unique label for that loop.
*
* Example:
*
* movi a3, 16 // loop 16 times
* floop a3, myloop1
* :
* bnez a7, end1 // exit loop if a7 != 0
* :
* floopend a3, myloop1
* end1:
*
* Like the LOOP instructions, these macros cannot be
* nested, must include at least one instruction,
* cannot call functions inside the loop, etc.
* The loop can be exited by jumping to the instruction
* following floopend (or elsewhere outside the loop),
* or continued by jumping to a NOP instruction placed
* immediately before floopend.
*
* Unlike LOOP instructions, the register passed to floop*
* cannot be used inside the loop, because it is used as
* the loop counter if the Loops option is not configured.
* And its value is undefined after exiting the loop.
* And because the loop counter register is active inside
* the loop, you can't easily use this construct to loop
* across a register file using ROTW as you might with LOOP
* instructions, unless you copy the loop register along.
*/
/* Named label version of the macros: */
.macro floop ar, endlabel
floop_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
.macro floopnez ar, endlabel
floopnez_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
.macro floopgtz ar, endlabel
floopgtz_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
.macro floopend ar, endlabel
floopend_ \ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
.endm
/* Numbered local label version of the macros: */
#if 0 /*UNTESTED*/
.macro floop89 ar
floop_ \ar, 8, 9f
.endm
.macro floopnez89 ar
floopnez_ \ar, 8, 9f
.endm
.macro floopgtz89 ar
floopgtz_ \ar, 8, 9f
.endm
.macro floopend89 ar
floopend_ \ar, 8b, 9
.endm
#endif /*0*/
/* Underlying version of the macros: */
.macro floop_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floop cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loop \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
\startlabel:
addi \ar, \ar, -1
#endif /* XCHAL_HAVE_LOOPS */
.endm // floop_
.macro floopnez_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floopnez cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loopnez \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
beqz \ar, \endlabelref
\startlabel:
addi \ar, \ar, -1
#endif /* XCHAL_HAVE_LOOPS */
.endm // floopnez_
.macro floopgtz_ ar, startlabel, endlabelref
.ifdef _infloop_
.if _infloop_
.err // Error: floopgtz cannot be nested
.endif
.endif
.set _infloop_, 1
#if XCHAL_HAVE_LOOPS
loopgtz \ar, \endlabelref
#else /* XCHAL_HAVE_LOOPS */
bltz \ar, \endlabelref
beqz \ar, \endlabelref
\startlabel:
addi \ar, \ar, -1
#endif /* XCHAL_HAVE_LOOPS */
.endm // floopgtz_
.macro floopend_ ar, startlabelref, endlabel
.ifndef _infloop_
.err // Error: floopend without matching floopXXX
.endif
.ifeq _infloop_
.err // Error: floopend without matching floopXXX
.endif
.set _infloop_, 0
#if ! XCHAL_HAVE_LOOPS
bnez \ar, \startlabelref
#endif /* XCHAL_HAVE_LOOPS */
\endlabel:
.endm // floopend_
/*----------------------------------------------------------------------
* crsil -- conditional RSIL (read/set interrupt level)
*
* Executes the RSIL instruction if it exists, else just reads PS.
* The RSIL instruction does not exist in the new exception architecture
* if the interrupt option is not selected.
*/
.macro crsil ar, newlevel
#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
rsil \ar, \newlevel
#else
rsr \ar, PS
#endif
.endm // crsil
/*----------------------------------------------------------------------
* window_spill{4,8,12}
*
* These macros spill callers' register windows to the stack.
* They work for both privileged and non-privileged tasks.
* Must be called from a windowed ABI context, eg. within
* a windowed ABI function (ie. valid stack frame, window
* exceptions enabled, not in exception mode, etc).
*
* This macro requires a single invocation of the window_spill_common
* macro in the same assembly unit and section.
*
* Note that using window_spill{4,8,12} macros is more efficient
* than calling a function implemented using window_spill_function,
* because the latter needs extra code to figure out the size of
* the call to the spilling function.
*
* Example usage:
*
* .text
* .align 4
* .global some_function
* .type some_function,@function
* some_function:
* entry a1, 16
* :
* :
*
* window_spill4 // spill windows of some_function's callers; preserves a0..a3 only;
* // to use window_spill{8,12} in this example function we'd have
* // to increase space allocated by the entry instruction, because
* // 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
* // for call8/window_spill8 or call12/window_spill12 respectively.
* :
*
* retw
*
* window_spill_common // instantiates code used by window_spill4
*
*
* On entry:
* none (if window_spill4)
* stack frame has enough space allocated for call8 (if window_spill8)
* stack frame has enough space allocated for call12 (if window_spill12)
* On exit:
* a4..a15 clobbered (if window_spill4)
* a8..a15 clobbered (if window_spill8)
* a12..a15 clobbered (if window_spill12)
* no caller windows are in live registers
*/
.macro window_spill4
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call4 .L__wdwspill_assist28 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call4 .L__wdwspill_assist60 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill4
.macro window_spill8
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call8 .L__wdwspill_assist24 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call8 .L__wdwspill_assist56 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill8
.macro window_spill12
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 16
movi a15, 0 // for 16-register files, no need to call to reach the end
# elif XCHAL_NUM_AREGS == 32
call12 .L__wdwspill_assist20 // call deep enough to clear out any live callers
# elif XCHAL_NUM_AREGS == 64
call12 .L__wdwspill_assist52 // call deep enough to clear out any live callers
# endif
#endif
.endm // window_spill12
/*----------------------------------------------------------------------
* window_spill_function
*
* This macro outputs a function that will spill its caller's callers'
* register windows to the stack. Eg. it could be used to implement
* a version of xthal_window_spill() that works in non-privileged tasks.
* This works for both privileged and non-privileged tasks.
*
* Typical usage:
*
* .text
* .align 4
* .global my_spill_function
* .type my_spill_function,@function
* my_spill_function:
* window_spill_function
*
* On entry to resulting function:
* none
* On exit from resulting function:
* none (no caller windows are in live registers)
*/
.macro window_spill_function
#if XCHAL_HAVE_WINDOWED
# if XCHAL_NUM_AREGS == 32
entry sp, 48
bbci.l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
call8 .L__wdwspill_assist16 // called with call8, only need another 8
retw
1: call12 .L__wdwspill_assist16 // called with call4, only need another 12
retw
2: call4 .L__wdwspill_assist16 // called with call12, only need another 4
retw
# elif XCHAL_NUM_AREGS == 64
entry sp, 48
bbci.l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
call4 .L__wdwspill_assist52 // called with call8, only need a call4
retw
1: call8 .L__wdwspill_assist52 // called with call4, only need a call8
retw
2: call12 .L__wdwspill_assist40 // called with call12, can skip a call12
retw
# elif XCHAL_NUM_AREGS == 16
entry sp, 16
bbci.l a0, 31, 1f // branch if called with call4
bbsi.l a0, 30, 2f // branch if called with call12
movi a7, 0 // called with call8
retw
1: movi a11, 0 // called with call4
2: retw // if called with call12, everything already spilled
// movi a15, 0 // trick to spill all but the direct caller
// j 1f
// // The entry instruction is magical in the assembler (gets auto-aligned)
// // so we have to jump to it to avoid falling through the padding.
// // We need entry/retw to know where to return.
//1: entry sp, 16
// retw
# else
# error "unrecognized address register file size"
# endif
#endif /* XCHAL_HAVE_WINDOWED */
window_spill_common
.endm // window_spill_function
/*----------------------------------------------------------------------
* window_spill_common
*
* Common code used by any number of invocations of the window_spill##
* and window_spill_function macros.
*
* Must be instantiated exactly once within a given assembly unit,
* within call/j range of and same section as window_spill##
* macro invocations for that assembly unit.
* (Is automatically instantiated by the window_spill_function macro.)
*/
.macro window_spill_common
#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
.ifndef .L__wdwspill_defined
# if XCHAL_NUM_AREGS >= 64
.L__wdwspill_assist60:
entry sp, 32
call8 .L__wdwspill_assist52
retw
.L__wdwspill_assist56:
entry sp, 16
call4 .L__wdwspill_assist52
retw
.L__wdwspill_assist52:
entry sp, 48
call12 .L__wdwspill_assist40
retw
.L__wdwspill_assist40:
entry sp, 48
call12 .L__wdwspill_assist28
retw
# endif
.L__wdwspill_assist28:
entry sp, 48
call12 .L__wdwspill_assist16
retw
.L__wdwspill_assist24:
entry sp, 32
call8 .L__wdwspill_assist16
retw
.L__wdwspill_assist20:
entry sp, 16
call4 .L__wdwspill_assist16
retw
.L__wdwspill_assist16:
entry sp, 16
movi a15, 0
retw
.set .L__wdwspill_defined, 1
.endif
#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
.endm // window_spill_common
/*----------------------------------------------------------------------
* beqi32
*
* macro implements version of beqi for arbitrary 32-bit immidiate value
*
* beqi32 ax, ay, imm32, label
*
* Compares value in register ax with imm32 value and jumps to label if
* equal. Clobberes register ay if needed
*
*/
.macro beqi32 ax, ay, imm, label
.ifeq ((\imm-1) & ~7) // 1..8 ?
beqi \ax, \imm, \label
.else
.ifeq (\imm+1) // -1 ?
beqi \ax, \imm, \label
.else
.ifeq (\imm) // 0 ?
beqz \ax, \label
.else
// We could also handle immediates 10,12,16,32,64,128,256
// but it would be a long macro...
movi \ay, \imm
beq \ax, \ay, \label
.endif
.endif
.endif
.endm // beqi32
#endif /*XTENSA_COREASM_H*/
include/asm-xtensa/xtensa/corebits.h 0 → 100644
浏览文件 @ e344b63e
#ifndef XTENSA_COREBITS_H
#define XTENSA_COREBITS_H
/*
* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
*
* xtensa/corebits.h - Xtensa Special Register field positions and masks.
*
* (In previous releases, these were defined in specreg.h, a generated file.
* This file is not generated, i.e. it is processor configuration independent.)
*/
/* EXCCAUSE register fields: */
#define EXCCAUSE_EXCCAUSE_SHIFT 0
#define EXCCAUSE_EXCCAUSE_MASK 0x3F
/* Exception causes (mostly incomplete!): */
#define EXCCAUSE_ILLEGAL 0
#define EXCCAUSE_SYSCALL 1
#define EXCCAUSE_IFETCHERROR 2
#define EXCCAUSE_LOADSTOREERROR 3
#define EXCCAUSE_LEVEL1INTERRUPT 4
#define EXCCAUSE_ALLOCA 5
/* PS register fields: */
#define PS_WOE_SHIFT 18
#define PS_WOE_MASK 0x00040000
#define PS_WOE PS_WOE_MASK
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_MASK 0x00030000
#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
#define PS_OWB_SHIFT 8
#define PS_OWB_MASK 0x00000F00
#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
#define PS_RING_SHIFT 6
#define PS_RING_MASK 0x000000C0
#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
#define PS_UM_SHIFT 5
#define PS_UM_MASK 0x00000020
#define PS_UM PS_UM_MASK
#define PS_EXCM_SHIFT 4
#define PS_EXCM_MASK 0x00000010
#define PS_EXCM PS_EXCM_MASK
#define PS_INTLEVEL_SHIFT 0
#define PS_INTLEVEL_MASK 0x0000000F
#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
/* Backward compatibility (deprecated): */
#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
#define PS_PROGSTACK_MASK PS_UM_MASK
#define PS_PROG_SHIFT PS_UM_SHIFT
#define PS_PROG_MASK PS_UM_MASK
#define PS_PROG PS_UM
/* DBREAKCn register fields: */
#define DBREAKC_MASK_SHIFT 0
#define DBREAKC_MASK_MASK 0x0000003F
#define DBREAKC_LOADBREAK_SHIFT 30
#define DBREAKC_LOADBREAK_MASK 0x40000000
#define DBREAKC_STOREBREAK_SHIFT 31
#define DBREAKC_STOREBREAK_MASK 0x80000000
/* DEBUGCAUSE register fields: */
#define DEBUGCAUSE_DEBUGINT_SHIFT 5
#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
#define DEBUGCAUSE_BREAKN_SHIFT 4
#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
#define DEBUGCAUSE_BREAK_SHIFT 3
#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
#define DEBUGCAUSE_DBREAK_SHIFT 2
#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
#define DEBUGCAUSE_IBREAK_SHIFT 1
#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
#define DEBUGCAUSE_ICOUNT_SHIFT 0
#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
#endif /*XTENSA_COREBITS_H*/
include/asm-xtensa/xtensa/hal.h 0 → 100644
浏览文件 @ e344b63e
此差异已折叠。
include/asm-xtensa/xtensa/simcall.h 0 → 100644
浏览文件 @ e344b63e
#ifndef SIMCALL_INCLUDED
#define SIMCALL_INCLUDED
/*
* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
*
* include/asm-xtensa/xtensa/simcall.h - Simulator call numbers
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of
* this archive for more details.
*
* Copyright (C) 2002 Tensilica Inc.
*/
/*
* System call like services offered by the simulator host.
* These are modeled after the Linux 2.4 kernel system calls
* for Xtensa processors. However not all system calls and
* not all functionality of a given system call are implemented,
* or necessarily have well defined or equivalent semantics in
* the context of a simulation (as opposed to a Unix kernel).
*
* These services behave largely as if they had been invoked
* as a task in the simulator host's operating system
* (eg. files accessed are those of the simulator host).
* However, these SIMCALLs model a virtual operating system
* so that various definitions, bit assignments etc
* (eg. open mode bits, errno values, etc) are independent
* of the host operating system used to run the simulation.
* Rather these definitions are specific to the Xtensa ISS.
* This way Xtensa ISA code written to use these SIMCALLs
* can (in principle) be simulated on any host.
*
* Up to 6 parameters are passed in registers a3 to a8
* (note the 6th parameter isn't passed on the stack,
* unlike windowed function calling conventions).
* The return value is in a2. A negative value in the
* range -4096 to -1 indicates a negated error code to be
* reported in errno with a return value of -1, otherwise
* the value in a2 is returned as is.
*/
/* These #defines need to match what's in Xtensa/OS/vxworks/xtiss/simcalls.c */
#define SYS_nop 0 /* n/a - setup; used to flush register windows */
#define SYS_exit 1 /*x*/
#define SYS_fork 2
#define SYS_read 3 /*x*/
#define SYS_write 4 /*x*/
#define SYS_open 5 /*x*/
#define SYS_close 6 /*x*/
#define SYS_rename 7 /*x 38 - waitpid */
#define SYS_creat 8 /*x*/
#define SYS_link 9 /*x (not implemented on WIN32) */
#define SYS_unlink 10 /*x*/
#define SYS_execv 11 /* n/a - execve */
#define SYS_execve 12 /* 11 - chdir */
#define SYS_pipe 13 /* 42 - time */
#define SYS_stat 14 /* 106 - mknod */
#define SYS_chmod 15
#define SYS_chown 16 /* 202 - lchown */
#define SYS_utime 17 /* 30 - break */
#define SYS_wait 18 /* n/a - oldstat */
#define SYS_lseek 19 /*x*/
#define SYS_getpid 20
#define SYS_isatty 21 /* n/a - mount */
#define SYS_fstat 22 /* 108 - oldumount */
#define SYS_time 23 /* 13 - setuid */
#define SYS_gettimeofday 24 /*x 78 - getuid (not implemented on WIN32) */
#define SYS_times 25 /*X 43 - stime (Xtensa-specific implementation) */
#define SYS_socket 26
#define SYS_sendto 27
#define SYS_recvfrom 28
#define SYS_select_one 29 /* not compitible select, one file descriptor at the time */
#define SYS_bind 30
#define SYS_ioctl 31
/*
* Other...
*/
#define SYS_iss_argc 1000 /* returns value of argc */
#define SYS_iss_argv_size 1001 /* bytes needed for argv & arg strings */
#define SYS_iss_set_argv 1002 /* saves argv & arg strings at given addr */
/*
* SIMCALLs for the ferret memory debugger. All are invoked by
* libferret.a ... ( Xtensa/Target-Libs/ferret )
*/
#define SYS_ferret 1010
#define SYS_malloc 1011
#define SYS_free 1012
#define SYS_more_heap 1013
#define SYS_no_heap 1014
/*
* Extra SIMCALLs for GDB:
*/
#define SYS_gdb_break -1 /* invoked by XTOS on user exceptions if EPC points
to a break.n/break, regardless of cause! */
#define SYS_xmon_out -2 /* invoked by XMON: ... */
#define SYS_xmon_in -3 /* invoked by XMON: ... */
#define SYS_xmon_flush -4 /* invoked by XMON: ... */
#define SYS_gdb_abort -5 /* invoked by XTOS in _xtos_panic() */
#define SYS_gdb_illegal_inst -6 /* invoked by XTOS for illegal instructions (too deeply) */
#define SYS_xmon_init -7 /* invoked by XMON: ... */
#define SYS_gdb_enter_sktloop -8 /* invoked by XTOS on debug exceptions */
/*
* SIMCALLs for vxWorks xtiss BSP:
*/
#define SYS_setup_ppp_pipes -83
#define SYS_log_msg -84
/*
* Test SIMCALLs:
*/
#define SYS_test_write_state -100
#define SYS_test_read_state -101
/*
* SYS_select_one specifiers
*/
#define XTISS_SELECT_ONE_READ 1
#define XTISS_SELECT_ONE_WRITE 2
#define XTISS_SELECT_ONE_EXCEPT 3
#endif /* !SIMCALL_INCLUDED */
include/asm-xtensa/xtensa/xt2000-uart.h 0 → 100644
浏览文件 @ e344b63e
#ifndef _uart_h_included_
#define _uart_h_included_
/*
* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
*
* include/asm-xtensa/xtensa/xt2000-uart.h -- NatSemi PC16552D DUART
* definitions
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002 Tensilica Inc.
*/
#include <xtensa/xt2000.h>
/* 16550 UART DEVICE REGISTERS
The XT2000 board aligns each register to a 32-bit word but the UART device only uses
one byte of the word, which is the least-significant byte regardless of the
endianness of the core (ie. byte offset 0 for little-endian and 3 for big-endian).
So if using word accesses then endianness doesn't matter.
The macros provided here do that.
*/
struct uart_dev_s {
union {
unsigned int rxb; /* DLAB=0: receive buffer, read-only */
unsigned int txb; /* DLAB=0: transmit buffer, write-only */
unsigned int dll; /* DLAB=1: divisor, least-significant byte latch (was write-only?) */
} w0;
union {
unsigned int ier; /* DLAB=0: interrupt-enable register (was write-only?) */
unsigned int dlm; /* DLAB=1: divisor, most-significant byte latch (was write-only?) */
} w1;
union {
unsigned int isr; /* DLAB=0: interrupt status register, read-only */
unsigned int fcr; /* DLAB=0: FIFO control register, write-only */
unsigned int afr; /* DLAB=1: alternate function register */
} w2;
unsigned int lcr; /* line control-register, write-only */
unsigned int mcr; /* modem control-regsiter, write-only */
unsigned int lsr; /* line status register, read-only */
unsigned int msr; /* modem status register, read-only */
unsigned int scr; /* scratch regsiter, read/write */
};
#define _RXB(u) ((u)->w0.rxb)
#define _TXB(u) ((u)->w0.txb)
#define _DLL(u) ((u)->w0.dll)
#define _IER(u) ((u)->w1.ier)
#define _DLM(u) ((u)->w1.dlm)
#define _ISR(u) ((u)->w2.isr)
#define _FCR(u) ((u)->w2.fcr)
#define _AFR(u) ((u)->w2.afr)
#define _LCR(u) ((u)->lcr)
#define _MCR(u) ((u)->mcr)
#define _LSR(u) ((u)->lsr)
#define _MSR(u) ((u)->msr)
#define _SCR(u) ((u)->scr)
typedef volatile struct uart_dev_s uart_dev_t;
/* IER bits */
#define RCVR_DATA_REG_INTENABLE 0x01
#define XMIT_HOLD_REG_INTENABLE 0x02
#define RCVR_STATUS_INTENABLE 0x04
#define MODEM_STATUS_INTENABLE 0x08
/* FCR bits */
#define _FIFO_ENABLE 0x01
#define RCVR_FIFO_RESET 0x02
#define XMIT_FIFO_RESET 0x04
#define DMA_MODE_SELECT 0x08
#define RCVR_TRIGGER_LSB 0x40
#define RCVR_TRIGGER_MSB 0x80
/* AFR bits */
#define AFR_CONC_WRITE 0x01
#define AFR_BAUDOUT_SEL 0x02
#define AFR_RXRDY_SEL 0x04
/* ISR bits */
#define INT_STATUS(r) ((r)&1)
#define INT_PRIORITY(r) (((r)>>1)&0x7)
/* LCR bits */
#define WORD_LENGTH(n) (((n)-5)&0x3)
#define STOP_BIT_ENABLE 0x04
#define PARITY_ENABLE 0x08
#define EVEN_PARITY 0x10
#define FORCE_PARITY 0x20
#define XMIT_BREAK 0x40
#define DLAB_ENABLE 0x80
/* MCR bits */
#define _DTR 0x01
#define _RTS 0x02
#define _OP1 0x04
#define _OP2 0x08
#define LOOP_BACK 0x10
/* LSR Bits */
#define RCVR_DATA_READY 0x01
#define OVERRUN_ERROR 0x02
#define PARITY_ERROR 0x04
#define FRAMING_ERROR 0x08
#define BREAK_INTERRUPT 0x10
#define XMIT_HOLD_EMPTY 0x20
#define XMIT_EMPTY 0x40
#define FIFO_ERROR 0x80
#define RCVR_READY(u) (_LSR(u)&RCVR_DATA_READY)
#define XMIT_READY(u) (_LSR(u)&XMIT_HOLD_EMPTY)
/* MSR bits */
#define _RDR 0x01
#define DELTA_DSR 0x02
#define DELTA_RI 0x04
#define DELTA_CD 0x08
#define _CTS 0x10
#define _DSR 0x20
#define _RI 0x40
#define _CD 0x80
/* prototypes */
void uart_init( uart_dev_t *u, int bitrate );
void uart_out( uart_dev_t *u, char c );
void uart_puts( uart_dev_t *u, char *s );
char uart_in( uart_dev_t *u );
void uart_enable_rcvr_int( uart_dev_t *u );
void uart_disable_rcvr_int( uart_dev_t *u );
#ifdef DUART16552_1_VADDR
/* DUART present. */
#define DUART_1_BASE (*(uart_dev_t*)DUART16552_1_VADDR)
#define DUART_2_BASE (*(uart_dev_t*)DUART16552_2_VADDR)
#define UART1_PUTS(s) uart_puts( &DUART_1_BASE, s )
#define UART2_PUTS(s) uart_puts( &DUART_2_BASE, s )
#else
/* DUART not configured, use dummy placeholders to allow compiles to work. */
#define DUART_1_BASE (*(uart_dev_t*)0)
#define DUART_2_BASE (*(uart_dev_t*)0)
#define UART1_PUTS(s)
#define UART2_PUTS(s)
#endif
/* Compute 16-bit divisor for baudrate generator, with rounding: */
#define DUART_DIVISOR(crystal,speed) (((crystal)/16 + (speed)/2)/(speed))
#endif /*_uart_h_included_*/
include/asm-xtensa/xtensa/xt2000.h 0 → 100644
浏览文件 @ e344b63e
此差异已折叠。
include/asm-xtensa/xtensa/xtboard.h 0 → 100644
浏览文件 @ e344b63e
此差异已折叠。
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