提交 dfdc2488 编写于 作者: L Linus Walleij

ARM: dts: Augment VGA connector bridge on Realview EB

The PL111 in the ARM reference platforms are connected to
"panels" that are actually dumb VGA DAC connector bridges.
Now that we can support the proper bridges in the DRM driver,
fix this up.

Cc: Mali DP Maintainers <malidp@foss.arm.com>
Reviewed-by: NLiviu Dudau <liviu.dudau@arm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
上级 3088a5c7
...@@ -143,6 +143,43 @@ ...@@ -143,6 +143,43 @@
port1-otg; port1-otg;
}; };
bridge {
compatible = "ti,ths8134a", "ti,ths8134";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
vga_bridge_in: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
port@1 {
reg = <1>;
vga_bridge_out: endpoint {
remote-endpoint = <&vga_con_in>;
};
};
};
};
vga {
compatible = "vga-connector";
port {
vga_con_in: endpoint {
remote-endpoint = <&vga_bridge_out>;
};
};
};
/* These peripherals are inside the FPGA */ /* These peripherals are inside the FPGA */
fpga { fpga {
#address-cells = <1>; #address-cells = <1>;
...@@ -409,36 +446,15 @@ ...@@ -409,36 +446,15 @@
interrupt-names = "combined"; interrupt-names = "combined";
clocks = <&oscclk0>, <&pclk>; clocks = <&oscclk0>, <&pclk>;
clock-names = "clcdclk", "apb_pclk"; clock-names = "clcdclk", "apb_pclk";
/* 1024x768 16bpp @65MHz works fine */
max-memory-bandwidth = <95000000>;
port { port {
clcd_pads: endpoint { clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>; remote-endpoint = <&vga_bridge_in>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
}; };
}; };
panel {
compatible = "panel-dpi";
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
/* Standard 640x480 VGA timings */
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <48>;
hfront-porch = <16>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <33>;
vfront-porch = <10>;
vsync-len = <2>;
};
};
}; };
}; };
}; };
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