提交 b6641294 编写于 作者: M Maarten Lankhorst 提交者: Thierry Reding

ARM: tegra: Enable watchdog support for Tegra114 and Tegra124

Watchdog support was added to the timer block with Tegra30. Tegra20 did
not have this yet. However, the Tegra114 and Tegra124 DTSI files had an
entry in the compatible string list for "nvidia,tegra20-timer", but not
for "nvidia,tegra30-timer", which is why watchdog support isn't enabled
on them.

Fix this by adding an entry for "nvidia,tegra30-timer" to the compatible
string list of the timer block on Tegra114 and Tegra124.

This allows the watchdog to work on Jetson TK1.
Signed-off-by: NMaarten Lankhorst <dev@mblankhorst.nl>
Signed-off-by: NThierry Reding <treding@nvidia.com>
上级 c90bb7b9
...@@ -150,7 +150,7 @@ ...@@ -150,7 +150,7 @@
}; };
timer@60005000 { timer@60005000 {
compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>; reg = <0x60005000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
......
...@@ -208,7 +208,7 @@ ...@@ -208,7 +208,7 @@
}; };
timer@0,60005000 { timer@0,60005000 {
compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x0 0x60005000 0x0 0x400>; reg = <0x0 0x60005000 0x0 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
......
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