提交 b31fc90c 编写于 作者: G Geert Uytterhoeven 提交者: Simon Horman

clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support

Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG)
driver using the generic PM Domain.  This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.

Also update the reg property in the DT binding doc example to match the
actual dtsi, which uses #address-cells and #size-cells == 1, not 2.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
上级 8bc964aa
* Renesas R8A7779 Clock Pulse Generator (CPG) * Renesas R8A7779 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7779. It includes one PLL and The CPG generates core clocks for the R8A7779. It includes one PLL and
several fixed ratio dividers several fixed ratio dividers.
The CPG also provides a Clock Domain for SoC devices, in combination with the
CPG Module Stop (MSTP) Clocks.
Required Properties: Required Properties:
...@@ -12,16 +14,36 @@ Required Properties: ...@@ -12,16 +14,36 @@ Required Properties:
- #clock-cells: Must be 1 - #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "plla", - clock-output-names: The names of the clocks. Supported clocks are "plla",
"z", "zs", "s", "s1", "p", "b", "out". "z", "zs", "s", "s1", "p", "b", "out".
- #power-domain-cells: Must be 0
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
through an MSTP clock should refer to the CPG device node in their
"power-domains" property, as documented by the generic PM domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.
Example
------- Examples
--------
- CPG device node:
cpg_clocks: cpg_clocks@ffc80000 { cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7779-cpg-clocks"; compatible = "renesas,r8a7779-cpg-clocks";
reg = <0 0xffc80000 0 0x30>; reg = <0xffc80000 0x30>;
clocks = <&extal_clk>; clocks = <&extal_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s", "s1", "p", clock-output-names = "plla", "z", "zs", "s", "s1", "p",
"b", "out"; "b", "out";
#power-domain-cells = <0>;
};
- CPG/MSTP Clock Domain member device node:
sata: sata@fc600000 {
compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
reg = <0xfc600000 0x2000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
power-domains = <&cpg_clocks>;
}; };
...@@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) ...@@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
} }
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
cpg_mstp_add_clk_domain(np);
} }
CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks", CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
r8a7779_cpg_clocks_init); r8a7779_cpg_clocks_init);
......
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