Skip to content

K
kernel_linux

OpenHarmony / kernel_linux
上一次同步 4 年多

通知 15
Star 8
Fork 2
K
kernel_linux
提交 b0f392c6 编写于 作者: T Tony Lindgren
浏览文件
操作

Merge tag 'omap-devel-a-for-3.11' of... 

Merge tag 'omap-devel-a-for-3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.11/omap5

Add support for the OMAP5 SoC family.

As part of the transition to DT, no board files will be used
for OMAP5.  The hwmod data is gradually being transitioned
away from arch/arm/mach-omap2: IRQ, DMA, and memory map data
has been moved to DT.  Hopefully the dev_attr and clock role
data will be the next step.

Basic test logs are available here, although not for OMAP5,
since I don't have an OMAP5 board:
http://www.pwsan.com/omap/testlogs/omap5_v3.10/20130608130949/
上级 317ddd25 e4020aa9
展开全部 隐藏空白更改
内联 并排
Showing with 8983 addition and 55 deletion
arch/arm/mach-omap2/Makefile
浏览文件 @ b0f392c6
...@@ -127,6 +127,7 @@ obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o ...@@ -127,6 +127,7 @@ obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
# OMAP powerdomain framework # OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o powerdomain-common += powerdomain.o powerdomain-common.o
...@@ -141,6 +142,7 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o ...@@ -141,6 +142,7 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
# PRCM clockdomain control # PRCM clockdomain control
clockdomain-common += clockdomain.o clockdomain-common += clockdomain.o
...@@ -156,6 +158,7 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o ...@@ -156,6 +158,7 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
# Clock framework # Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
...@@ -198,6 +201,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o ...@@ -198,6 +201,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
# EMU peripherals # EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o obj-$(CONFIG_OMAP3_EMU) += emu.o
......
arch/arm/mach-omap2/clockdomain.h
浏览文件 @ b0f392c6
...@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void); ...@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void); extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm); extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm); extern void clkdm_del_autodeps(struct clockdomain *clkdm);
......
arch/arm/mach-omap2/clockdomains54xx_data.c 0 → 100644
浏览文件 @ b0f392c6
/*
* OMAP54XX Clock domains framework
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include "clockdomain.h"
#include "cm1_54xx.h"
#include "cm2_54xx.h"
#include "cm-regbits-54xx.h"
#include "prm54xx.h"
#include "prcm44xx.h"
#include "prcm_mpu54xx.h"
/* Static Dependencies for OMAP4 Clock Domains */
static struct clkdm_dep c2c_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ NULL },
};
static struct clkdm_dep cam_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ NULL },
};
static struct clkdm_dep dma_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep dsp_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep dss_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ NULL },
};
static struct clkdm_dep gpu_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ NULL },
};
static struct clkdm_dep ipu_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "dsp_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep iva_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ NULL },
};
static struct clkdm_dep l3init_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ NULL },
};
static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ NULL },
};
static struct clkdm_dep mpu_wkup_sleep_deps[] = {
{ .clkdm_name = "abe_clkdm" },
{ .clkdm_name = "dsp_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l3main2_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clockdomain l4sec_54xx_clkdm = {
.name = "l4sec_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
.dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4sec_wkup_sleep_deps,
.sleepdep_srcs = l4sec_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain iva_54xx_clkdm = {
.name = "iva_clkdm",
.pwrdm = { .name = "iva_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_IVA_INST,
.clkdm_offs = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
.dep_bit = OMAP54XX_IVA_STATDEP_SHIFT,
.wkdep_srcs = iva_wkup_sleep_deps,
.sleepdep_srcs = iva_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain mipiext_54xx_clkdm = {
.name = "mipiext_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
.wkdep_srcs = mipiext_wkup_sleep_deps,
.sleepdep_srcs = mipiext_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain l3main2_54xx_clkdm = {
.name = "l3main2_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
.dep_bit = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
};
static struct clockdomain l3main1_54xx_clkdm = {
.name = "l3main1_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
.dep_bit = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
};
static struct clockdomain custefuse_54xx_clkdm = {
.name = "custefuse_clkdm",
.pwrdm = { .name = "custefuse_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain ipu_54xx_clkdm = {
.name = "ipu_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
.dep_bit = OMAP54XX_IPU_STATDEP_SHIFT,
.wkdep_srcs = ipu_wkup_sleep_deps,
.sleepdep_srcs = ipu_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain l4cfg_54xx_clkdm = {
.name = "l4cfg_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
.dep_bit = OMAP54XX_L4CFG_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
};
static struct clockdomain abe_54xx_clkdm = {
.name = "abe_clkdm",
.pwrdm = { .name = "abe_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_AON_ABE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
.dep_bit = OMAP54XX_ABE_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain dss_54xx_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "dss_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_DSS_INST,
.clkdm_offs = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
.dep_bit = OMAP54XX_DSS_STATDEP_SHIFT,
.wkdep_srcs = dss_wkup_sleep_deps,
.sleepdep_srcs = dss_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain dsp_54xx_clkdm = {
.name = "dsp_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_AON_DSP_INST,
.clkdm_offs = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
.dep_bit = OMAP54XX_DSP_STATDEP_SHIFT,
.wkdep_srcs = dsp_wkup_sleep_deps,
.sleepdep_srcs = dsp_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain c2c_54xx_clkdm = {
.name = "c2c_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
.wkdep_srcs = c2c_wkup_sleep_deps,
.sleepdep_srcs = c2c_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain l4per_54xx_clkdm = {
.name = "l4per_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
.dep_bit = OMAP54XX_L4PER_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain gpu_54xx_clkdm = {
.name = "gpu_clkdm",
.pwrdm = { .name = "gpu_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_GPU_INST,
.clkdm_offs = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
.dep_bit = OMAP54XX_GPU_STATDEP_SHIFT,
.wkdep_srcs = gpu_wkup_sleep_deps,
.sleepdep_srcs = gpu_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain wkupaon_54xx_clkdm = {
.name = "wkupaon_clkdm",
.pwrdm = { .name = "wkupaon_pwrdm" },
.prcm_partition = OMAP54XX_PRM_PARTITION,
.cm_inst = OMAP54XX_PRM_WKUPAON_CM_INST,
.clkdm_offs = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
.dep_bit = OMAP54XX_WKUPAON_STATDEP_SHIFT,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain mpu0_54xx_clkdm = {
.name = "mpu0_clkdm",
.pwrdm = { .name = "cpu0_pwrdm" },
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.cm_inst = OMAP54XX_PRCM_MPU_CM_C0_INST,
.clkdm_offs = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain mpu1_54xx_clkdm = {
.name = "mpu1_clkdm",
.pwrdm = { .name = "cpu1_pwrdm" },
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.cm_inst = OMAP54XX_PRCM_MPU_CM_C1_INST,
.clkdm_offs = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain coreaon_54xx_clkdm = {
.name = "coreaon_clkdm",
.pwrdm = { .name = "coreaon_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_COREAON_INST,
.clkdm_offs = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain mpu_54xx_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_AON_MPU_INST,
.clkdm_offs = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
.wkdep_srcs = mpu_wkup_sleep_deps,
.sleepdep_srcs = mpu_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain l3init_54xx_clkdm = {
.name = "l3init_clkdm",
.pwrdm = { .name = "l3init_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_L3INIT_INST,
.clkdm_offs = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
.dep_bit = OMAP54XX_L3INIT_STATDEP_SHIFT,
.wkdep_srcs = l3init_wkup_sleep_deps,
.sleepdep_srcs = l3init_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain dma_54xx_clkdm = {
.name = "dma_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
.wkdep_srcs = dma_wkup_sleep_deps,
.sleepdep_srcs = dma_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain l3instr_54xx_clkdm = {
.name = "l3instr_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
};
static struct clockdomain emif_54xx_clkdm = {
.name = "emif_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CORE_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
.dep_bit = OMAP54XX_EMIF_STATDEP_SHIFT,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain emu_54xx_clkdm = {
.name = "emu_clkdm",
.pwrdm = { .name = "emu_pwrdm" },
.prcm_partition = OMAP54XX_PRM_PARTITION,
.cm_inst = OMAP54XX_PRM_EMU_CM_INST,
.clkdm_offs = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain cam_54xx_clkdm = {
.name = "cam_clkdm",
.pwrdm = { .name = "cam_pwrdm" },
.prcm_partition = OMAP54XX_CM_CORE_PARTITION,
.cm_inst = OMAP54XX_CM_CORE_CAM_INST,
.clkdm_offs = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
.wkdep_srcs = cam_wkup_sleep_deps,
.sleepdep_srcs = cam_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
/* As clockdomains are added or removed above, this list must also be changed */
static struct clockdomain *clockdomains_omap54xx[] __initdata = {
&l4sec_54xx_clkdm,
&iva_54xx_clkdm,
&mipiext_54xx_clkdm,
&l3main2_54xx_clkdm,
&l3main1_54xx_clkdm,
&custefuse_54xx_clkdm,
&ipu_54xx_clkdm,
&l4cfg_54xx_clkdm,
&abe_54xx_clkdm,
&dss_54xx_clkdm,
&dsp_54xx_clkdm,
&c2c_54xx_clkdm,
&l4per_54xx_clkdm,
&gpu_54xx_clkdm,
&wkupaon_54xx_clkdm,
&mpu0_54xx_clkdm,
&mpu1_54xx_clkdm,
&coreaon_54xx_clkdm,
&mpu_54xx_clkdm,
&l3init_54xx_clkdm,
&dma_54xx_clkdm,
&l3instr_54xx_clkdm,
&emif_54xx_clkdm,
&emu_54xx_clkdm,
&cam_54xx_clkdm,
NULL
};
void __init omap54xx_clockdomains_init(void)
{
clkdm_register_platform_funcs(&omap4_clkdm_operations);
clkdm_register_clkdms(clockdomains_omap54xx);
clkdm_complete_init();
}
arch/arm/mach-omap2/cm-regbits-54xx.h 0 → 100644
浏览文件 @ b0f392c6
此差异已折叠。
arch/arm/mach-omap2/cm1_44xx.h
浏览文件 @ b0f392c6
...@@ -25,6 +25,8 @@ ...@@ -25,6 +25,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
#include "cm_44xx_54xx.h"
/* CM1 base address */ /* CM1 base address */
#define OMAP4430_CM1_BASE 0x4a004000 #define OMAP4430_CM1_BASE 0x4a004000
...@@ -217,9 +219,4 @@ ...@@ -217,9 +219,4 @@
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
/* Function prototypes */
extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
#endif #endif
arch/arm/mach-omap2/cm1_54xx.h 0 → 100644
浏览文件 @ b0f392c6
/*
* OMAP54xx CM1 instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
#include "cm_44xx_54xx.h"
/* CM1 base address */
#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
/* CM_CORE_AON instances */
#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
#define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
#define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
#define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
#define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
#define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
#define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
/* CM_CORE_AON clockdomain register offsets (from instance start) */
#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000
/* CM_CORE_AON */
/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000
#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080
#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084
#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090
#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094
#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098
#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c
#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0
#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4
#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8
#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac
#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0
#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4
#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8
#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc
#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0
#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4
#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8
#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc
#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0
#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4
#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8
#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc
#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0
#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4
#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8
#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec
#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0
/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
#define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000
#define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
#define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008
#define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
#define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010
#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
#define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
#define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
#define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
#define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
#define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
#define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
#define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
#define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
#define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
#define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
#define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
#define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
#define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
#define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
#define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
#define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
#define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
#define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
#define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
#define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
#define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8
#define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc
#define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
#define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
#define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
#define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
#define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
#define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
#define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
#define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180
/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004
#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004
#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008
#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028
#define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030
#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038
#define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040
#define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060
#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088
#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
#endif
arch/arm/mach-omap2/cm2_44xx.h
浏览文件 @ b0f392c6
...@@ -25,6 +25,8 @@ ...@@ -25,6 +25,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
#include "cm_44xx_54xx.h"
/* CM2 base address */ /* CM2 base address */
#define OMAP4430_CM2_BASE 0x4a008000 #define OMAP4430_CM2_BASE 0x4a008000
...@@ -449,9 +451,4 @@ ...@@ -449,9 +451,4 @@
#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
/* Function prototypes */
extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
#endif #endif
arch/arm/mach-omap2/cm2_54xx.h 0 → 100644
浏览文件 @ b0f392c6
此差异已折叠。
arch/arm/mach-omap2/cm_44xx_54xx.h 0 → 100644
浏览文件 @ b0f392c6
/*
* OMAP44xx and OMAP54xx CM1/CM2 function prototypes
*
* Copyright (C) 2009-2013 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
/* CM1 Function prototypes */
extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
/* CM2 Function prototypes */
extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
#endif
arch/arm/mach-omap2/io.c
浏览文件 @ b0f392c6
...@@ -631,7 +631,13 @@ void __init omap5_init_early(void) ...@@ -631,7 +631,13 @@ void __init omap5_init_early(void)
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap_prm_base_init(); omap_prm_base_init();
omap_cm_base_init(); omap_cm_base_init();
omap44xx_prm_init();
omap5xxx_check_revision(); omap5xxx_check_revision();
omap54xx_voltagedomains_init();
omap54xx_powerdomains_init();
omap54xx_clockdomains_init();
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
} }
#endif #endif
......
arch/arm/mach-omap2/omap_hwmod.h
浏览文件 @ b0f392c6
...@@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void); ...@@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void); extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void); extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void); extern int omap44xx_hwmod_init(void);
extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void); extern int am33xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
......
arch/arm/mach-omap2/omap_hwmod_54xx_data.c 0 → 100644
浏览文件 @ b0f392c6
此差异已折叠。
arch/arm/mach-omap2/powerdomain.h
浏览文件 @ b0f392c6
...@@ -253,6 +253,7 @@ extern void omap243x_powerdomains_init(void); ...@@ -253,6 +253,7 @@ extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void); extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void); extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void);
extern void omap54xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations; extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations; extern struct pwrdm_ops omap3_pwrdm_operations;
......
arch/arm/mach-omap2/powerdomains54xx_data.c 0 → 100644
浏览文件 @ b0f392c6
/*
* OMAP54XX Power domains framework
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include "powerdomain.h"
#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm-regbits-54xx.h"
#include "prm54xx.h"
#include "prcm_mpu54xx.h"
/* core_54xx_pwrdm: CORE power domain */
static struct powerdomain core_54xx_pwrdm = {
.name = "core_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_CORE_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRSTS_OFF_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRSTS_OFF_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* abe_54xx_pwrdm: Audio back end power domain */
static struct powerdomain abe_54xx_pwrdm = {
.name = "abe_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_ABE_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* aessmem */
[1] = PWRSTS_OFF_RET, /* periphmem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* aessmem */
[1] = PWRSTS_OFF_RET, /* periphmem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
static struct powerdomain coreaon_54xx_pwrdm = {
.name = "coreaon_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_COREAON_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
};
/* dss_54xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_54xx_pwrdm = {
.name = "dss_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_DSS_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dss_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dss_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_54xx_pwrdm = {
.name = "cpu0_pwrdm",
.voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cpu0_l1 */
},
};
/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_54xx_pwrdm = {
.name = "cpu1_pwrdm",
.voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
.prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cpu1_l1 */
},
};
/* emu_54xx_pwrdm: Emulation power domain */
static struct powerdomain emu_54xx_pwrdm = {
.name = "emu_pwrdm",
.voltdm = { .name = "wkup" },
.prcm_offs = OMAP54XX_PRM_EMU_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* emu_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* emu_bank */
},
};
/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_54xx_pwrdm = {
.name = "mpu_pwrdm",
.voltdm = { .name = "mpu" },
.prcm_offs = OMAP54XX_PRM_MPU_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
[1] = PWRSTS_RET, /* mpu_ram */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
[1] = PWRSTS_OFF_RET, /* mpu_ram */
},
};
/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_54xx_pwrdm = {
.name = "custefuse_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* dsp_54xx_pwrdm: Tesla processor power domain */
static struct powerdomain dsp_54xx_pwrdm = {
.name = "dsp_pwrdm",
.voltdm = { .name = "mm" },
.prcm_offs = OMAP54XX_PRM_DSP_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dsp_edma */
[1] = PWRSTS_OFF_RET, /* dsp_l1 */
[2] = PWRSTS_OFF_RET, /* dsp_l2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dsp_edma */
[1] = PWRSTS_OFF_RET, /* dsp_l1 */
[2] = PWRSTS_OFF_RET, /* dsp_l2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* cam_54xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_54xx_pwrdm = {
.name = "cam_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_CAM_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cam_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* cam_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l3init_54xx_pwrdm: L3 initators pheripherals power domain */
static struct powerdomain l3init_54xx_pwrdm = {
.name = "l3init_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = OMAP54XX_PRM_L3INIT_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* l3init_bank1 */
[1] = PWRSTS_OFF_RET, /* l3init_bank2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* l3init_bank1 */
[1] = PWRSTS_OFF_RET, /* l3init_bank2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* gpu_54xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gpu_54xx_pwrdm = {
.name = "gpu_pwrdm",
.voltdm = { .name = "mm" },
.prcm_offs = OMAP54XX_PRM_GPU_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* gpu_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* gpu_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* wkupaon_54xx_pwrdm: Wake-up power domain */
static struct powerdomain wkupaon_54xx_pwrdm = {
.name = "wkupaon_pwrdm",
.voltdm = { .name = "wkup" },
.prcm_offs = OMAP54XX_PRM_WKUPAON_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
.banks = 1,
.pwrsts_mem_ret = {
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* wkup_bank */
},
};
/* iva_54xx_pwrdm: IVA-HD power domain */
static struct powerdomain iva_54xx_pwrdm = {
.name = "iva_pwrdm",
.voltdm = { .name = "mm" },
.prcm_offs = OMAP54XX_PRM_IVA_INST,
.prcm_partition = OMAP54XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 4,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* hwa_mem */
[1] = PWRSTS_OFF_RET, /* sl2_mem */
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* hwa_mem */
[1] = PWRSTS_OFF_RET, /* sl2_mem */
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/*
* The following power domains are not under SW control
*
* mpuaon
* mmaon
*/
/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap54xx[] __initdata = {
&core_54xx_pwrdm,
&abe_54xx_pwrdm,
&coreaon_54xx_pwrdm,
&dss_54xx_pwrdm,
&cpu0_54xx_pwrdm,
&cpu1_54xx_pwrdm,
&emu_54xx_pwrdm,
&mpu_54xx_pwrdm,
&custefuse_54xx_pwrdm,
&dsp_54xx_pwrdm,
&cam_54xx_pwrdm,
&l3init_54xx_pwrdm,
&gpu_54xx_pwrdm,
&wkupaon_54xx_pwrdm,
&iva_54xx_pwrdm,
NULL
};
void __init omap54xx_powerdomains_init(void)
{
pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_omap54xx);
pwrdm_complete_init();
}
arch/arm/mach-omap2/prcm44xx.h
浏览文件 @ b0f392c6
...@@ -32,6 +32,12 @@ ...@@ -32,6 +32,12 @@
#define OMAP4430_SCRM_PARTITION 4 #define OMAP4430_SCRM_PARTITION 4
#define OMAP4430_PRCM_MPU_PARTITION 5 #define OMAP4430_PRCM_MPU_PARTITION 5
#define OMAP54XX_PRM_PARTITION 1
#define OMAP54XX_CM_CORE_AON_PARTITION 2
#define OMAP54XX_CM_CORE_PARTITION 3
#define OMAP54XX_SCRM_PARTITION 4
#define OMAP54XX_PRCM_MPU_PARTITION 5
/* /*
* OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
* IDs, plus one * IDs, plus one
......
arch/arm/mach-omap2/prcm_mpu44xx.h
浏览文件 @ b0f392c6
...@@ -25,12 +25,9 @@ ...@@ -25,12 +25,9 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
#include "prcm_mpu_44xx_54xx.h"
#include "common.h" #include "common.h"
# ifndef __ASSEMBLER__
extern void __iomem *prcm_mpu_base;
# endif
#define OMAP4430_PRCM_MPU_BASE 0x48243000 #define OMAP4430_PRCM_MPU_BASE 0x48243000
#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
...@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base; ...@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base;
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
/* Function prototypes */
# ifndef __ASSEMBLER__
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
s16 idx);
extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
# endif
#endif #endif
arch/arm/mach-omap2/prcm_mpu54xx.h 0 → 100644
浏览文件 @ b0f392c6
/*
* OMAP54xx PRCM MPU instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
#include "prcm_mpu_44xx_54xx.h"
#include "common.h"
#define OMAP54XX_PRCM_MPU_BASE 0x48243000
#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
/* PRCM_MPU instances */
#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
#define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
#define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
#define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
#define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
#define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
/* PRCM_MPU clockdomain register offsets (from instance start) */
#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
/*
* PRCM_MPU
*
* The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
* point of view the PRCM_MPU is a single entity. It shares the same
* programming model as the global PRCM and thus can be assimilate as two new
* MOD inside the PRCM
*/
/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
#define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004
#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
#endif
arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h 0 → 100644
浏览文件 @ b0f392c6
/*
* OMAP44xx and OMAP54xx PRCM MPU function prototypes
*
* Copyright (C) 2010, 2013 Texas Instruments, Inc.
* Copyright (C) 2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
#ifndef __ASSEMBLER__
extern void __iomem *prcm_mpu_base;
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
s16 idx);
extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
#endif
#endif
arch/arm/mach-omap2/prm-regbits-54xx.h 0 → 100644
浏览文件 @ b0f392c6
此差异已折叠。
arch/arm/mach-omap2/prm44xx.h
浏览文件 @ b0f392c6
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
#include "prm44xx_54xx.h"
#include "prcm-common.h" #include "prcm-common.h"
#include "prm.h" #include "prm.h"
...@@ -744,36 +745,4 @@ ...@@ -744,36 +745,4 @@
#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
/* Function prototypes */
# ifndef __ASSEMBLER__
extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
/* OMAP4-specific VP functions */
u32 omap4_prm_vp_check_txdone(u8 vp_id);
void omap4_prm_vp_clear_txdone(u8 vp_id);
/*
* OMAP4 access functions for voltage controller (VC) and
* voltage proccessor (VP) in the PRM.
*/
extern u32 omap4_prm_vcvp_read(u8 offset);
extern void omap4_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
extern void omap44xx_prm_reconfigure_io_chain(void);
/* PRM interrupt-related functions */
extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
extern void omap44xx_prm_ocp_barrier(void);
extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
extern int __init omap44xx_prm_init(void);
extern u32 omap44xx_prm_get_reset_sources(void);
# endif
#endif #endif
arch/arm/mach-omap2/prm44xx_54xx.h 0 → 100644
浏览文件 @ b0f392c6
/*
* OMAP44xx and 54xx PRM common functions
*
* Copyright (C) 2009-2013 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
/* Function prototypes */
#ifndef __ASSEMBLER__
extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
/* OMAP4/OMAP5-specific VP functions */
u32 omap4_prm_vp_check_txdone(u8 vp_id);
void omap4_prm_vp_clear_txdone(u8 vp_id);
/*
* OMAP4/OMAP5 access functions for voltage controller (VC) and
* voltage proccessor (VP) in the PRM.
*/
extern u32 omap4_prm_vcvp_read(u8 offset);
extern void omap4_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
extern void omap44xx_prm_reconfigure_io_chain(void);
/* PRM interrupt-related functions */
extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
extern void omap44xx_prm_ocp_barrier(void);
extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
extern int __init omap44xx_prm_init(void);
extern u32 omap44xx_prm_get_reset_sources(void);
#endif
#endif
arch/arm/mach-omap2/prm54xx.h 0 → 100644
浏览文件 @ b0f392c6
此差异已折叠。
arch/arm/mach-omap2/scrm54xx.h 0 → 100644
浏览文件 @ b0f392c6
/*
* OMAP54XX SCRM registers and bitfields
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
#define OMAP5_SCRM_BASE 0x4ae0a000
#define OMAP54XX_SCRM_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
/* SCRM */
/* SCRM.SCRM register offsets */
#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000
#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000)
#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100
#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100)
#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104
#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104)
#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110
#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110)
#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118
#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118)
#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c
#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c)
#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200
#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200)
#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204
#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204)
#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208
#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208)
#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210
#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210)
#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214
#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214)
#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218
#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218)
#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c
#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c)
#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220
#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220)
#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224
#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224)
#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234
#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234)
#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310
#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310)
#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314
#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314)
#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318
#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318)
#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c
#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c)
#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320
#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320)
#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324
#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324)
#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400
#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400)
#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418
#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418)
#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c
#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c)
#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420)
#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510
#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510)
#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514
#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514)
#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518
#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518)
#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c
#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c)
/*
* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
* AUXCLKREQ5, D2DCLKREQ
*/
#define OMAP5_ACCURACY_SHIFT 1
#define OMAP5_ACCURACY_WIDTH 0x1
#define OMAP5_ACCURACY_MASK (1 << 1)
/* Used by APEWARMRSTST */
#define OMAP5_APEWARMRSTST_SHIFT 1
#define OMAP5_APEWARMRSTST_WIDTH 0x1
#define OMAP5_APEWARMRSTST_MASK (1 << 1)
/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
#define OMAP5_CLKDIV_SHIFT 16
#define OMAP5_CLKDIV_WIDTH 0x4
#define OMAP5_CLKDIV_MASK (0xf << 16)
/* Used by D2DCLKM, MODEMCLKM */
#define OMAP5_CLK_32KHZ_SHIFT 0
#define OMAP5_CLK_32KHZ_WIDTH 0x1
#define OMAP5_CLK_32KHZ_MASK (1 << 0)
/* Used by D2DRSTCTRL, MODEMRSTCTRL */
#define OMAP5_COLDRST_SHIFT 0
#define OMAP5_COLDRST_WIDTH 0x1
#define OMAP5_COLDRST_MASK (1 << 0)
/* Used by D2DWARMRSTST */
#define OMAP5_D2DWARMRSTST_SHIFT 3
#define OMAP5_D2DWARMRSTST_WIDTH 0x1
#define OMAP5_D2DWARMRSTST_MASK (1 << 3)
/* Used by AUXCLK0 */
#define OMAP5_DISABLECLK_SHIFT 9
#define OMAP5_DISABLECLK_WIDTH 0x1
#define OMAP5_DISABLECLK_MASK (1 << 9)
/* Used by CLKSETUPTIME */
#define OMAP5_DOWNTIME_SHIFT 16
#define OMAP5_DOWNTIME_WIDTH 0x6
#define OMAP5_DOWNTIME_MASK (0x3f << 16)
/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
#define OMAP5_ENABLE_SHIFT 8
#define OMAP5_ENABLE_WIDTH 0x1
#define OMAP5_ENABLE_MASK (1 << 8)
/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
#define OMAP5_ENABLE_0_0_SHIFT 0
#define OMAP5_ENABLE_0_0_WIDTH 0x1
#define OMAP5_ENABLE_0_0_MASK (1 << 0)
/* Used by ALTCLKSRC */
#define OMAP5_ENABLE_EXT_SHIFT 3
#define OMAP5_ENABLE_EXT_WIDTH 0x1
#define OMAP5_ENABLE_EXT_MASK (1 << 3)
/* Used by ALTCLKSRC */
#define OMAP5_ENABLE_INT_SHIFT 2
#define OMAP5_ENABLE_INT_WIDTH 0x1
#define OMAP5_ENABLE_INT_MASK (1 << 2)
/* Used by EXTWARMRSTST */
#define OMAP5_EXTWARMRSTST_SHIFT 0
#define OMAP5_EXTWARMRSTST_WIDTH 0x1
#define OMAP5_EXTWARMRSTST_MASK (1 << 0)
/*
* Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
* AUXCLKREQ5
*/
#define OMAP5_MAPPING_SHIFT 2
#define OMAP5_MAPPING_WIDTH 0x3
#define OMAP5_MAPPING_MASK (0x7 << 2)
/* Used by ALTCLKSRC */
#define OMAP5_MODE_SHIFT 0
#define OMAP5_MODE_WIDTH 0x2
#define OMAP5_MODE_MASK (0x3 << 0)
/* Used by MODEMWARMRSTST */
#define OMAP5_MODEMWARMRSTST_SHIFT 2
#define OMAP5_MODEMWARMRSTST_WIDTH 0x1
#define OMAP5_MODEMWARMRSTST_MASK (1 << 2)
/*
* Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
* AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
* D2DCLKREQ, EXTCLKREQ, PWRREQ
*/
#define OMAP5_POLARITY_SHIFT 0
#define OMAP5_POLARITY_WIDTH 0x1
#define OMAP5_POLARITY_MASK (1 << 0)
/* Used by EXTPWRONRSTCTRL */
#define OMAP5_PWRONRST_SHIFT 1
#define OMAP5_PWRONRST_WIDTH 0x1
#define OMAP5_PWRONRST_MASK (1 << 1)
/* Used by REVISION_SCRM */
#define OMAP5_REV_SHIFT 0
#define OMAP5_REV_WIDTH 0x8
#define OMAP5_REV_MASK (0xff << 0)
/* Used by RSTTIME */
#define OMAP5_RSTTIME_SHIFT 0
#define OMAP5_RSTTIME_WIDTH 0x4
#define OMAP5_RSTTIME_MASK (0xf << 0)
/* Used by CLKSETUPTIME */
#define OMAP5_SETUPTIME_SHIFT 0
#define OMAP5_SETUPTIME_WIDTH 0xc
#define OMAP5_SETUPTIME_MASK (0xfff << 0)
/* Used by PMICSETUPTIME */
#define OMAP5_SLEEPTIME_SHIFT 0
#define OMAP5_SLEEPTIME_WIDTH 0x6
#define OMAP5_SLEEPTIME_MASK (0x3f << 0)
/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
#define OMAP5_SRCSELECT_SHIFT 1
#define OMAP5_SRCSELECT_WIDTH 0x2
#define OMAP5_SRCSELECT_MASK (0x3 << 1)
/* Used by D2DCLKM */
#define OMAP5_SYSCLK_SHIFT 1
#define OMAP5_SYSCLK_WIDTH 0x1
#define OMAP5_SYSCLK_MASK (1 << 1)
/* Used by PMICSETUPTIME */
#define OMAP5_WAKEUPTIME_SHIFT 16
#define OMAP5_WAKEUPTIME_WIDTH 0x6
#define OMAP5_WAKEUPTIME_MASK (0x3f << 16)
/* Used by D2DRSTCTRL, MODEMRSTCTRL */
#define OMAP5_WARMRST_SHIFT 1
#define OMAP5_WARMRST_WIDTH 0x1
#define OMAP5_WARMRST_MASK (1 << 1)
#endif
arch/arm/mach-omap2/voltage.h
浏览文件 @ b0f392c6
...@@ -171,6 +171,7 @@ extern void omap2xxx_voltagedomains_init(void); ...@@ -171,6 +171,7 @@ extern void omap2xxx_voltagedomains_init(void);
extern void omap3xxx_voltagedomains_init(void); extern void omap3xxx_voltagedomains_init(void);
extern void am33xx_voltagedomains_init(void); extern void am33xx_voltagedomains_init(void);
extern void omap44xx_voltagedomains_init(void); extern void omap44xx_voltagedomains_init(void);
extern void omap54xx_voltagedomains_init(void);
struct voltagedomain *voltdm_lookup(const char *name); struct voltagedomain *voltdm_lookup(const char *name);
void voltdm_init(struct voltagedomain **voltdm_list); void voltdm_init(struct voltagedomain **voltdm_list);
......
arch/arm/mach-omap2/voltagedomains54xx_data.c 0 → 100644
浏览文件 @ b0f392c6
/*
* OMAP5 Voltage Management Routines
*
* Based on voltagedomains44xx_data.c
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/init.h>
#include "common.h"
#include "prm54xx.h"
#include "voltage.h"
#include "omap_opp_data.h"
#include "vc.h"
#include "vp.h"
static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = {
.voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
};
static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = {
.voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET,
};
static const struct omap_vfsm_instance omap5_vdd_core_vfsm = {
.voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
};
static struct voltagedomain omap5_voltdm_mpu = {
.name = "mpu",
.scalable = true,
.read = omap4_prm_vcvp_read,
.write = omap4_prm_vcvp_write,
.rmw = omap4_prm_vcvp_rmw,
.vc = &omap4_vc_mpu,
.vfsm = &omap5_vdd_mpu_vfsm,
.vp = &omap4_vp_mpu,
};
static struct voltagedomain omap5_voltdm_mm = {
.name = "mm",
.scalable = true,
.read = omap4_prm_vcvp_read,
.write = omap4_prm_vcvp_write,
.rmw = omap4_prm_vcvp_rmw,
.vc = &omap4_vc_iva,
.vfsm = &omap5_vdd_mm_vfsm,
.vp = &omap4_vp_iva,
};
static struct voltagedomain omap5_voltdm_core = {
.name = "core",
.scalable = true,
.read = omap4_prm_vcvp_read,
.write = omap4_prm_vcvp_write,
.rmw = omap4_prm_vcvp_rmw,
.vc = &omap4_vc_core,
.vfsm = &omap5_vdd_core_vfsm,
.vp = &omap4_vp_core,
};
static struct voltagedomain omap5_voltdm_wkup = {
.name = "wkup",
};
static struct voltagedomain *voltagedomains_omap5[] __initdata = {
&omap5_voltdm_mpu,
&omap5_voltdm_mm,
&omap5_voltdm_core,
&omap5_voltdm_wkup,
NULL,
};
static const char *sys_clk_name __initdata = "sys_clkin";
void __init omap54xx_voltagedomains_init(void)
{
struct voltagedomain *voltdm;
int i;
/*
* XXX Will depend on the process, validation, and binning
* for the currently-running IC. Use OMAP4 data for time being.
*/
#ifdef CONFIG_PM_OPP
omap5_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
omap5_voltdm_mm.volt_data = omap446x_vdd_iva_volt_data;
omap5_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
#endif
for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++)
voltdm->sys_clk.name = sys_clk_name;
voltdm_init(voltagedomains_omap5);
};
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或