drm/i915: restore render clock gating on resume

Rather than restoring just a few clock gating registers on resume,
just reinitialize the whole thing.
Signed-off-by: NAndy Lutomirski <luto@mit.edu>
[anholt: Fixed up for RC6 support landed since the patch was written]
Signed-off-by: NEric Anholt <eric@anholt.net>

drivers/gpu/drm/i915/i915_drv.h

@@ -381,8 +381,6 @@ typedef struct drm_i915_private {
 	u32 saveFDI_RXA_IMR;
 	u32 saveFDI_RXB_IMR;
 	u32 saveCACHE_MODE_0;
-	u32 saveD_STATE;
-	u32 saveDSPCLK_GATE_D;
 	u32 saveMI_ARB_STATE;
 	u32 saveSWF0[16];
 	u32 saveSWF1[16];

drivers/gpu/drm/i915/i915_suspend.c

@@ -722,10 +722,6 @@ int i915_save_state(struct drm_device *dev)
 		dev_priv->saveIMR = I915_READ(IMR);
 	}
 
-	/* Clock gating state */
-	dev_priv->saveD_STATE = I915_READ(D_STATE);
-	dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */
-
 	/* Cache mode state */
 	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
@@ -800,8 +796,7 @@ int i915_restore_state(struct drm_device *dev)
 	}
 
 	/* Clock gating state */
-	I915_WRITE (D_STATE, dev_priv->saveD_STATE);
-	I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
+	intel_init_clock_gating(dev);
 
 	/* Cache mode state */
 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);

drivers/gpu/drm/i915/intel_display.c

@@ -4584,28 +4584,33 @@ void intel_init_clock_gating(struct drm_device *dev)
 		struct drm_i915_gem_object *obj_priv;
 		int ret;
 
-		pwrctx = drm_gem_object_alloc(dev, 4096);
-		if (!pwrctx) {
-			DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
-			goto out;
-		}
+		if (dev_priv->pwrctx) {
+			obj_priv = dev_priv->pwrctx->driver_private;
+		} else {
+			pwrctx = drm_gem_object_alloc(dev, 4096);
+			if (!pwrctx) {
+				DRM_DEBUG("failed to alloc power context, "
+					  "RC6 disabled\n");
+				goto out;
+			}
 
-		ret = i915_gem_object_pin(pwrctx, 4096);
-		if (ret) {
-			DRM_ERROR("failed to pin power context: %d\n", ret);
-			drm_gem_object_unreference(pwrctx);
-			goto out;
-		}
+			ret = i915_gem_object_pin(pwrctx, 4096);
+			if (ret) {
+				DRM_ERROR("failed to pin power context: %d\n",
+					  ret);
+				drm_gem_object_unreference(pwrctx);
+				goto out;
+			}
 
-		i915_gem_object_set_to_gtt_domain(pwrctx, 1);
+			i915_gem_object_set_to_gtt_domain(pwrctx, 1);
 
-		obj_priv = pwrctx->driver_private;
+			dev_priv->pwrctx = pwrctx;
+			obj_priv = pwrctx->driver_private;
+		}
 
 		I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
 		I915_WRITE(MCHBAR_RENDER_STANDBY,
 			   I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
-
-		dev_priv->pwrctx = pwrctx;
 	}
 
 out:

drivers/gpu/drm/i915/intel_drv.h

@@ -208,6 +208,7 @@ extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 				    u16 blue, int regno);
 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 				    u16 *blue, int regno);
+extern void intel_init_clock_gating(struct drm_device *dev);
 
 extern int intel_framebuffer_create(struct drm_device *dev,
 				    struct drm_mode_fb_cmd *mode_cmd,