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kernel_linux
提交 773d7a09 编写于 作者: L Linus Torvalds
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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (35 commits)
  powerpc/5121: make clock debug output more readable
  powerpc/5xxx: Add common mpc5xxx_get_bus_frequency() function
  powerpc/5200: Update pcm030.dts to add i2c eeprom and delete cruft
  powerpc/5200: convert mpc52xx_psc_spi to use cs_control callback
  fbdev/xilinxfb: Fix improper casting and tighen up probe path
  usb/ps3: Add missing annotations
  powerpc: Add memory clobber to mtspr()
  powerpc: Fix invalid construct in our CPU selection Kconfig
  ps3rom: Use ps3_system_bus_[gs]et_drvdata() instead of direct access
  powerpc: Add configurable -Werror for arch/powerpc
  of_serial: Add UPF_FIXED_TYPE flag
  drivers/hvc: Add missing __devexit_p()
  net/ps3: gelic - Add missing annotations
  powerpc: Introduce macro spin_event_timeout()
  powerpc/warp: Fix ISA_DMA_THRESHOLD default
  powerpc/bootwrapper: Custom build options for XPedite52xx targets
  powerpc/85xx: Add defconfig for X-ES MPC85xx boards
  powerpc/85xx: Add dts files for X-ES MPC85xx boards
  powerpc/85xx: Add platform support for X-ES MPC85xx boards
  83xx: add support for the kmeter1 board.
  ...
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arch/powerpc/Kconfig.debug
浏览文件 @ 773d7a09
......@@ -2,6 +2,23 @@ menu "Kernel hacking"
source "lib/Kconfig.debug"
config PPC_DISABLE_WERROR
bool "Don't build arch/powerpc code with -Werror"
default n
help
This option tells the compiler NOT to build the code under
arch/powerpc with the -Werror flag (which means warnings
are treated as errors).
Only enable this if you are hitting a build failure in the
arch/powerpc code caused by a warning, and you don't feel
inclined to fix it.
config PPC_WERROR
bool
depends on !PPC_DISABLE_WERROR
default y
config PRINT_STACK_DEPTH
int "Stack depth to print" if DEBUG_KERNEL
default 64
......
arch/powerpc/boot/cuboot-85xx.c
浏览文件 @ 773d7a09
......@@ -15,6 +15,7 @@
#include "cuboot.h"
#define TARGET_85xx
#define TARGET_HAS_ETH3
#include "ppcboot.h"
static bd_t bd;
......@@ -27,6 +28,7 @@ static void platform_fixups(void)
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr);
dt_fixup_mac_address_by_alias("ethernet3", bd.bi_enet3addr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq);
/* Unfortunately, the specific model number is encoded in the
......
arch/powerpc/boot/dts/asp834x-redboot.dts
浏览文件 @ 773d7a09
......@@ -167,7 +167,7 @@
interrupt-parent = <&ipic>;
interrupts = <39 0x8>;
phy_type = "ulpi";
port1;
port0;
};
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {
......
arch/powerpc/boot/dts/gef_sbc610.dts
浏览文件 @ 773d7a09
......@@ -152,6 +152,16 @@
interrupt-parent = <&mpic>;
dfsrr;
hwmon@48 {
compatible = "national,lm92";
reg = <0x48>;
};
hwmon@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
rtc@51 {
compatible = "epson,rx8581";
reg = <0x00000051>;
......
arch/powerpc/boot/dts/kmeter1.dts 0 → 100644
浏览文件 @ 773d7a09
/*
* Keymile KMETER1 Device Tree Source
*
* 2008 DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "KMETER1";
compatible = "keymile,KMETER1";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
ethernet1 = &enet_estar1;
ethernet2 = &enet_estar2;
ethernet3 = &enet_eth1;
ethernet4 = &enet_eth2;
ethernet5 = &enet_eth3;
ethernet6 = &enet_eth4;
serial0 = &serial0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8360@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; /* Filled in by U-Boot */
bus-frequency = <0>; /* Filled in by U-Boot */
clock-frequency = <0>; /* Filled in by U-Boot */
};
};
memory {
device_type = "memory";
reg = <0 0>; /* Filled in by U-Boot */
};
soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8360-immr", "simple-bus";
ranges = <0x0 0xe0000000 0x00200000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>; /* Filled in by U-Boot */
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <264000000>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "fsl,pq2pro-pic", "fsl,ipic";
interrupt-controller;
reg = <0x700 0x100>;
};
par_io@1400 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1400 0x100>;
compatible = "fsl,mpc8360-par_io";
num-ports = <7>;
pio_ucc1: ucc_pin@0 {
reg = <0>;
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
0 3 1 0 1 0 /* TxD0 */
0 4 1 0 1 0 /* TxD1 */
0 5 1 0 1 0 /* TxD2 */
0 6 1 0 1 0 /* TxD3 */
0 9 2 0 1 0 /* RxD0 */
0 10 2 0 1 0 /* RxD1 */
0 11 2 0 1 0 /* RxD2 */
0 12 2 0 1 0 /* RxD3 */
0 7 1 0 1 0 /* TX_EN */
0 8 1 0 1 0 /* TX_ER */
0 15 2 0 1 0 /* RX_DV */
0 16 2 0 1 0 /* RX_ER */
0 0 2 0 1 0 /* RX_CLK */
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
2 8 2 0 1 0 /* GTX125 - CLK9 */
>;
};
pio_ucc2: ucc_pin@1 {
reg = <1>;
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
0 17 1 0 1 0 /* TxD0 */
0 18 1 0 1 0 /* TxD1 */
0 19 1 0 1 0 /* TxD2 */
0 20 1 0 1 0 /* TxD3 */
0 23 2 0 1 0 /* RxD0 */
0 24 2 0 1 0 /* RxD1 */
0 25 2 0 1 0 /* RxD2 */
0 26 2 0 1 0 /* RxD3 */
0 21 1 0 1 0 /* TX_EN */
0 22 1 0 1 0 /* TX_ER */
0 29 2 0 1 0 /* RX_DV */
0 30 2 0 1 0 /* RX_ER */
0 31 2 0 1 0 /* RX_CLK */
2 2 1 0 2 0 /* GTX_CLK - CLK3 */
2 3 2 0 1 0 /* GTX125 - CLK4 */
>;
};
pio_ucc4: ucc_pin@3 {
reg = <3>;
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_ucc5: ucc_pin@4 {
reg = <4>;
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
>;
};
pio_ucc6: ucc_pin@5 {
reg = <5>;
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
>;
};
pio_ucc7: ucc_pin@6 {
reg = <6>;
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
>;
};
pio_ucc8: ucc_pin@7 {
reg = <7>;
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
>;
};
};
qe@100000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe";
ranges = <0x0 0x100000 0x100000>;
reg = <0x100000 0x480>;
clock-frequency = <0>; /* Filled in by U-Boot */
brg-frequency = <0>; /* Filled in by U-Boot */
bus-frequency = <0>; /* Filled in by U-Boot */
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x00010000 0x0000c000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0xc000>;
};
};
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
enet_estar1: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk9";
phy-handle = <&phy_estar1>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio_ucc1>;
};
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
enet_estar2: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <2>;
reg = <0x3000 0x200>;
interrupts = <33>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk4";
phy-handle = <&phy_estar2>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio_ucc2>;
};
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
enet_piggy2: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk17";
phy-handle = <&phy_piggy2>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc4>;
};
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
enet_eth1: ucc@2400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <5>;
reg = <0x2400 0x200>;
interrupts = <40>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth1>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc5>;
};
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
enet_eth2: ucc@3400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <6>;
reg = <0x3400 0x200>;
interrupts = <41>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth2>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc6>;
};
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
enet_eth3: ucc@2600 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <7>;
reg = <0x2600 0x200>;
interrupts = <42>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth3>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc7>;
};
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
enet_eth4: ucc@3600 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <8>;
reg = <0x3600 0x200>;
interrupts = <43>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth4>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc8>;
};
mdio@3320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3320 0x18>;
compatible = "fsl,ucc-mdio";
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
phy_piggy2: ethernet-phy@00 {
reg = <0x0>;
};
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
phy_eth1: ethernet-phy@08 {
reg = <0x08>;
};
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
phy_eth2: ethernet-phy@09 {
reg = <0x09>;
};
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
phy_eth3: ethernet-phy@0a {
reg = <0x0a>;
};
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
phy_eth4: ethernet-phy@0b {
reg = <0x0b>;
};
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
phy_estar1: ethernet-phy@10 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x10>;
};
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
phy_estar2: ethernet-phy@11 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x11>;
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
interrupts = <32 8 33 8>;
interrupt-parent = <&ipic>;
};
};
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */
flash@f0000000,0 {
compatible = "cfi-flash";
/*
* The Intel P30 chip has 2 non-identical chips on
* one die, so we need to define 2 seperate regions
* that are scanned by physmap_of independantly.
*/
reg = <0 0x00000000 0x02000000
0 0x02000000 0x02000000>; /* Filled in by U-Boot */
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0 0x40000>;
};
partition@40000 {
label = "env";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "dtb";
reg = <0x80000 0x20000>;
};
partition@a0000 {
label = "kernel";
reg = <0xa0000 0x300000>;
};
partition@3a0000 {
label = "ramdisk";
reg = <0x3a0000 0x800000>;
};
partition@ba0000 {
label = "user";
reg = <0xba0000 0x3460000>;
};
};
};
};
arch/powerpc/boot/dts/mpc8272ads.dts
浏览文件 @ 773d7a09
......@@ -17,6 +17,13 @@
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
serial0 = &scc1;
serial1 = &scc4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
......@@ -46,13 +53,13 @@
#size-cells = <1>;
reg = <0xf0010100 0x40>;
ranges = <0x0 0x0 0xfe000000 0x2000000
ranges = <0x0 0x0 0xff800000 0x00800000
0x1 0x0 0xf4500000 0x8000
0x3 0x0 0xf8200000 0x8000>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0x0 0x0 0x2000000>;
reg = <0x0 0x0 0x00800000>;
bank-width = <4>;
device-width = <1>;
};
......@@ -144,7 +151,7 @@
reg = <0x119f0 0x10 0x115f0 0x10>;
};
serial@11a00 {
scc1: serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
......@@ -155,7 +162,7 @@
fsl,cpm-command = <0x800000>;
};
serial@11a60 {
scc4: serial@11a60 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
......@@ -192,7 +199,7 @@
};
};
ethernet@11300 {
eth0: ethernet@11300 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
......@@ -205,7 +212,7 @@
fsl,cpm-command = <0x12000300>;
};
ethernet@11320 {
eth1: ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
......
arch/powerpc/boot/dts/mpc8315erdb.dts
浏览文件 @ 773d7a09
......@@ -322,6 +322,21 @@
reg = <0x700 0x100>;
device_type = "ipic";
};
ipic-msi@7c0 {
compatible = "fsl,ipic-msi";
reg = <0x7c0 0x40>;
msi-available-ranges = <0 0x100>;
interrupts = <0x43 0x8
0x4 0x8
0x51 0x8
0x52 0x8
0x56 0x8
0x57 0x8
0x58 0x8
0x59 0x8>;
interrupt-parent = < &ipic >;
};
};
pci0: pci@e0008500 {
......
arch/powerpc/boot/dts/mpc8349emitx.dts
浏览文件 @ 773d7a09
......@@ -156,7 +156,7 @@
interrupt-parent = <&ipic>;
interrupts = <39 0x8>;
phy_type = "ulpi";
port1;
port0;
};
usb@23000 {
......
arch/powerpc/boot/dts/mpc834x_mds.dts
浏览文件 @ 773d7a09
......@@ -153,7 +153,7 @@
interrupt-parent = <&ipic>;
interrupts = <39 0x8>;
phy_type = "ulpi";
port1;
port0;
};
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {
......
arch/powerpc/boot/dts/mpc8377_mds.dts
浏览文件 @ 773d7a09
......@@ -155,7 +155,7 @@
};
sdhci@2e000 {
compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
......
arch/powerpc/boot/dts/mpc8377_rdb.dts
浏览文件 @ 773d7a09
......@@ -169,7 +169,7 @@
};
sdhci@2e000 {
compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
......
arch/powerpc/boot/dts/mpc8378_mds.dts
浏览文件 @ 773d7a09
......@@ -155,7 +155,7 @@
};
sdhci@2e000 {
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
......
arch/powerpc/boot/dts/mpc8378_rdb.dts
浏览文件 @ 773d7a09
......@@ -169,7 +169,7 @@
};
sdhci@2e000 {
compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
......
arch/powerpc/boot/dts/mpc8379_mds.dts
浏览文件 @ 773d7a09
......@@ -153,7 +153,7 @@
};
sdhci@2e000 {
compatible = "fsl,mpc8379-esdhc";
compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
......
arch/powerpc/boot/dts/mpc8379_rdb.dts
浏览文件 @ 773d7a09
......@@ -167,7 +167,7 @@
};
sdhci@2e000 {
compatible = "fsl,mpc8379-esdhc";
compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
......
arch/powerpc/boot/dts/mpc8569mds.dts
浏览文件 @ 773d7a09
......@@ -24,6 +24,8 @@
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
ethernet5 = &enet5;
ethernet7 = &enet7;
pci1 = &pci1;
rapidio0 = &rio0;
};
......@@ -70,8 +72,30 @@
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x02000000>;
bank-width = <2>;
bank-width = <1>;
device-width = <1>;
partition@0 {
label = "ramdisk";
reg = <0x00000000 0x01c00000>;
};
partition@1c00000 {
label = "kernel";
reg = <0x01c00000 0x002e0000>;
};
partiton@1ee0000 {
label = "dtb";
reg = <0x01ee0000 0x00020000>;
};
partition@1f00000 {
label = "firmware";
reg = <0x01f00000 0x00080000>;
read-only;
};
partition@1f80000 {
label = "u-boot";
reg = <0x01f80000 0x00080000>;
read-only;
};
};
bcsr@1,0 {
......@@ -466,6 +490,37 @@
reg = <0x3>;
device_type = "ethernet-phy";
};
qe_phy5: ethernet-phy@04 {
interrupt-parent = <&mpic>;
reg = <0x04>;
device_type = "ethernet-phy";
};
qe_phy7: ethernet-phy@06 {
interrupt-parent = <&mpic>;
reg = <0x6>;
device_type = "ethernet-phy";
};
};
mdio@3520 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3520 0x18>;
compatible = "fsl,ucc-mdio";
tbi0: tbi-phy@15 {
reg = <0x15>;
device_type = "tbi-phy";
};
};
mdio@3720 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3720 0x38>;
compatible = "fsl,ucc-mdio";
tbi1: tbi-phy@17 {
reg = <0x17>;
device_type = "tbi-phy";
};
};
enet2: ucc@2200 {
......@@ -513,6 +568,36 @@
phy-connection-type = "rgmii-id";
};
enet5: ucc@3400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <6>;
reg = <0x3400 0x200>;
interrupts = <41>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "none";
tbi-handle = <&tbi0>;
phy-handle = <&qe_phy5>;
phy-connection-type = "sgmii";
};
enet7: ucc@3600 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <8>;
reg = <0x3600 0x200>;
interrupts = <43>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "none";
tbi-handle = <&tbi1>;
phy-handle = <&qe_phy7>;
phy-connection-type = "sgmii";
};
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
......
arch/powerpc/boot/dts/pcm030.dts
浏览文件 @ 773d7a09
......@@ -258,34 +258,16 @@
compatible = "nxp,pcf8563";
reg = <0x51>;
};
/* FIXME: EEPROM */
eeprom@52 {
compatible = "catalyst,24c32";
reg = <0x52>;
};
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
/* This is only an example device to show the usage of gpios. It maps all available
* gpios to the "gpio-provider" device.
*/
gpio {
compatible = "gpio-provider";
/* mpc52xx exp.con patchfield */
gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */
&gpio_wkup 1 0 /* GPIO_WKUP_6 14c */
&gpio_wkup 6 0 /* PSC2_4 43c x5-11 */
&gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */
&gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */
&gpt2 0 0 /* timer2 12d x4-4 */
&gpt3 0 0 /* timer3 13d x6-4 */
&gpt4 0 0 /* timer4 61c x2-16 */
&gpt5 0 0 /* timer5 44c x7-11 */
&gpt6 0 0 /* timer6 60c x8-15 */
&gpt7 0 0 /* timer7 36a x17-9 */
>;
};
};
pci@f0000d00 {
......
arch/powerpc/boot/dts/sbc8349.dts
浏览文件 @ 773d7a09
......@@ -144,7 +144,7 @@
interrupt-parent = <&ipic>;
interrupts = <39 0x8>;
phy_type = "ulpi";
port1;
port0;
};
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {
......
arch/powerpc/boot/dts/xcalibur1501.dts 0 → 100644
浏览文件 @ 773d7a09
/*
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
*
* XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/ {
model = "xes,xcalibur1501";
compatible = "xes,xcalibur1501", "xes,MPC8572";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8572@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
PowerPC,8572@1 {
device_type = "cpu";
reg = <0x1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
};
localbus@ef005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xef005000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
/* Local bus region mappings */
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */
1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */
4 0 0 0xe9000000 0x100000>; /* CS4: USB */
nor-boot@0,0 {
compatible = "amd,s29gl01gp", "cfi-flash";
bank-width = <2>;
reg = <0 0 0x8000000>; /* 128MB */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Primary user space";
reg = <0x00000000 0x6f00000>; /* 111 MB */
};
partition@6f00000 {
label = "Primary kernel";
reg = <0x6f00000 0x1000000>; /* 16 MB */
};
partition@7f00000 {
label = "Primary DTB";
reg = <0x7f00000 0x40000>; /* 256 KB */
};
partition@7f40000 {
label = "Primary U-Boot environment";
reg = <0x7f40000 0x40000>; /* 256 KB */
};
partition@7f80000 {
label = "Primary U-Boot";
reg = <0x7f80000 0x80000>; /* 512 KB */
read-only;
};
};
nor-alternate@1,0 {
compatible = "amd,s29gl01gp", "cfi-flash";
bank-width = <2>;
//reg = <0xf0000000 0x08000000>; /* 128MB */
reg = <1 0 0x8000000>; /* 128MB */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Secondary user space";
reg = <0x00000000 0x6f00000>; /* 111 MB */
};
partition@6f00000 {
label = "Secondary kernel";
reg = <0x6f00000 0x1000000>; /* 16 MB */
};
partition@7f00000 {
label = "Secondary DTB";
reg = <0x7f00000 0x40000>; /* 256 KB */
};
partition@7f40000 {
label = "Secondary U-Boot environment";
reg = <0x7f40000 0x40000>; /* 256 KB */
};
partition@7f80000 {
label = "Secondary U-Boot";
reg = <0x7f80000 0x80000>; /* 512 KB */
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
/*
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
* Micron MT29F8G08DAA (2x 512 MB), or Micron
* MT29F16G08FAA (2x 1 GB), depending on the build
* configuration
*/
compatible = "fsl,mpc8572-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <2 0 0x40000>;
/* U-Boot should fix this up if chip size > 1 GB */
partition@0 {
label = "NAND Filesystem";
reg = <0 0x40000000>;
};
};
usb@4,0 {
compatible = "nxp,usb-isp1761";
reg = <4 0 0x100000>;
bus-width = <32>;
interrupt-parent = <&mpic>;
interrupts = <10 1>;
};
};
soc8572@ef000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8572-immr", "simple-bus";
ranges = <0x0 0 0xef000000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x6000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x100000>; // L2, 1M
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
temp-sensor@48 {
compatible = "dallas,ds1631", "dallas,ds1621";
reg = <0x48>;
};
temp-sensor@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
cpu-supervisor@51 {
compatible = "dallas,ds4510";
reg = <0x51>;
};
eeprom@54 {
compatible = "atmel,at24c128b";
reg = <0x54>;
};
rtc@68 {
compatible = "stm,m41t00",
"dallas,ds1338";
reg = <0x68>;
};
pcie-switch@6a {
compatible = "plx,pex8648";
reg = <0x6a>;
};
/* On-board signals for VID, flash, serial */
gpio1: gpio@18 {
compatible = "nxp,pca9557";
reg = <0x18>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
/* PMC0/XMC0 signals */
gpio2: gpio@1c {
compatible = "nxp,pca9557";
reg = <0x1c>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
/* PMC1/XMC1 signals */
gpio3: gpio@1d {
compatible = "nxp,pca9557";
reg = <0x1d>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
/* CompactPCI signals (sysen, GA[4:0]) */
gpio4: gpio@1e {
compatible = "nxp,pca9557";
reg = <0x1e>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
/* CompactPCI J5 GPIO and FAL/DEG/PRST */
gpio5: gpio@1f {
compatible = "nxp,pca9557";
reg = <0x1f>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0xc300 0x4>;
ranges = <0x0 0xc100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
/* eTSEC 1 front panel 0 */
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <4 1>;
reg = <0x1>;
};
phy1: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <4 1>;
reg = <0x2>;
};
phy2: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0x3>;
};
phy3: ethernet-phy@4 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0x4>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC 2 front panel 1 */
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC 3 PICMG2.16 backplane port 0 */
enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC 4 PICMG2.16 backplane port 1 */
enet3: ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* UART0 */
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
/* UART1 */
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
msi@41600 {
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
crypto@30000 {
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
"fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x9fe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
gpio0: gpio@f000 {
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x1000>;
interrupts = <47 2>;
interrupt-parent = <&mpic>;
#gpio-cells = <2>;
gpio-controller;
};
gpio-leds {
compatible = "gpio-leds";
heartbeat {
label = "Heartbeat";
gpios = <&gpio0 4 1>;
linux,default-trigger = "heartbeat";
};
yellow {
label = "Yellow";
gpios = <&gpio0 5 1>;
};
red {
label = "Red";
gpios = <&gpio0 6 1>;
};
green {
label = "Green";
gpios = <&gpio0 7 1>;
};
};
/* PME (pattern-matcher) */
pme@10000 {
compatible = "fsl,mpc8572-pme", "pme8572";
reg = <0x10000 0x5000>;
interrupts = <57 2 64 2 65 2 66 2 67 2>;
interrupt-parent = <&mpic>;
};
tlu@2f000 {
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
reg = <0x2f000 0x1000>;
interupts = <61 2 >;
interrupt-parent = <&mpic>;
};
tlu@15000 {
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
reg = <0x15000 0x1000>;
interupts = <75 2>;
interrupt-parent = <&mpic>;
};
};
/*
* PCI Express controller 3 @ ef008000 is not used.
* This would have been pci0 on other mpc85xx platforms.
*
* PCI Express controller 2 @ ef009000 is not used.
* This would have been pci1 on other mpc85xx platforms.
*/
/* PCI Express controller 1, wired to PEX8648 PCIe switch */
pci2: pcie@ef00a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xef00a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x40000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
arch/powerpc/boot/dts/xpedite5200.dts 0 → 100644
浏览文件 @ 773d7a09
/*
* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
* Based on TQM8548 device tree
*
* XPedite5200 PrPMC/XMC module based on MPC8548E
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/ {
model = "xes,xpedite5200";
compatible = "xes,xpedite5200", "xes,MPC8548";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8548@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0>; // Filled in by U-Boot
};
soc@ef000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0x0 0xef000000 0x100000>;
bus-frequency = <0>;
compatible = "fsl,mpc8548-immr", "simple-bus";
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,mpc8548-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8548-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
/* On-card I2C */
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
/*
* Board GPIO:
* 0: BRD_CFG0 (1: P14 IO present)
* 1: BRD_CFG1 (1: FP ethernet present)
* 2: BRD_CFG2 (1: XMC IO present)
* 3: XMC root complex indicator
* 4: Flash boot device indicator
* 5: Flash write protect enable
* 6: PMC monarch indicator
* 7: PMC EREADY
*/
gpio1: gpio@18 {
compatible = "nxp,pca9556";
reg = <0x18>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
/* P14 GPIO */
gpio2: gpio@19 {
compatible = "nxp,pca9556";
reg = <0x19>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
eeprom@50 {
compatible = "atmel,at24c16";
reg = <0x50>;
};
rtc@68 {
compatible = "stm,m41t00",
"dallas,ds1338";
reg = <0x68>;
};
dtt@48 {
compatible = "maxim,max1237";
reg = <0x34>;
};
};
/* Off-card I2C */
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
/* eTSEC1: Front panel port 0 */
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x1>;
};
phy1: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x2>;
};
phy2: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x3>;
};
phy3: ethernet-phy@4 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x4>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC2: Front panel port 1 */
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC3: Rear panel port 2 */
enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC4: Rear panel port 3 */
enet3: ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
current-speed = <115200>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
current-speed = <115200>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { // global utilities reg
compatible = "fsl,mpc8548-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
};
localbus@ef005000 {
compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
"simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xef005000 0x100>; // BRx, ORx, etc.
ranges = <
0 0x0 0xfc000000 0x04000000 // NOR boot flash
1 0x0 0xf8000000 0x04000000 // NOR expansion flash
2 0x0 0xef800000 0x00010000 // NAND CE1
3 0x0 0xef840000 0x00010000 // NAND CE2
>;
nor-boot@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0 0x0 0x4000000>;
bank-width = <2>;
partition@0 {
label = "Primary OS";
reg = <0x00000000 0x180000>;
};
partition@180000 {
label = "Secondary OS";
reg = <0x00180000 0x180000>;
};
partition@300000 {
label = "User";
reg = <0x00300000 0x3c80000>;
};
partition@3f80000 {
label = "Boot firmware";
reg = <0x03f80000 0x80000>;
};
};
nor-alternate@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <1 0x0 0x4000000>;
bank-width = <2>;
partition@0 {
label = "Filesystem";
reg = <0x00000000 0x3f80000>;
};
partition@3f80000 {
label = "Alternate boot firmware";
reg = <0x03f80000 0x80000>;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xes,address-ctl-nand";
reg = <2 0x0 0x10000>;
cle-line = <0x8>; /* CLE tied to A3 */
ale-line = <0x10>; /* ALE tied to A4 */
/* U-Boot should fix this up */
partition@0 {
label = "NAND Filesystem";
reg = <0 0x40000000>;
};
};
};
/* PMC interface */
pci0: pci@ef008000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
reg = <0xef008000 0x1000>;
clock-frequency = <33333333>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
};
/* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
};
arch/powerpc/boot/dts/xpedite5200_xmon.dts 0 → 100644
浏览文件 @ 773d7a09
/*
* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
* Based on TQM8548 device tree
*
* XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the
* xMon boot loader memory map which differs from U-Boot's.
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/ {
model = "xes,xpedite5200";
compatible = "xes,xpedite5200", "xes,MPC8548";
#address-cells = <1>;
#size-cells = <1>;
form-factor = "PMC/XMC";
boot-bank = <0x0>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8548@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0>; // Filled in by boot loader
};
soc@ef000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0x0 0xef000000 0x100000>;
bus-frequency = <0>;
compatible = "fsl,mpc8548-immr", "simple-bus";
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,mpc8548-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8548-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
/* On-card I2C */
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
/*
* Board GPIO:
* 0: BRD_CFG0 (1: P14 IO present)
* 1: BRD_CFG1 (1: FP ethernet present)
* 2: BRD_CFG2 (1: XMC IO present)
* 3: XMC root complex indicator
* 4: Flash boot device indicator
* 5: Flash write protect enable
* 6: PMC monarch indicator
* 7: PMC EREADY
*/
gpio1: gpio@18 {
compatible = "nxp,pca9556";
reg = <0x18>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
/* P14 GPIO */
gpio2: gpio@19 {
compatible = "nxp,pca9556";
reg = <0x19>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
eeprom@50 {
compatible = "atmel,at24c16";
reg = <0x50>;
};
rtc@68 {
compatible = "stm,m41t00",
"dallas,ds1338";
reg = <0x68>;
};
dtt@48 {
compatible = "maxim,max1237";
reg = <0x34>;
};
};
/* Off-card I2C */
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
/* eTSEC1: Front panel port 0 */
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x1>;
};
phy1: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x2>;
};
phy2: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x3>;
};
phy3: ethernet-phy@4 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x4>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC2: Front panel port 1 */
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC3: Rear panel port 2 */
enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC4: Rear panel port 3 */
enet3: ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
current-speed = <9600>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
current-speed = <9600>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { // global utilities reg
compatible = "fsl,mpc8548-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
};
localbus@ef005000 {
compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
"simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xef005000 0x100>; // BRx, ORx, etc.
ranges = <
0 0x0 0xf8000000 0x08000000 // NOR boot flash
1 0x0 0xf0000000 0x08000000 // NOR expansion flash
2 0x0 0xe8000000 0x00010000 // NAND CE1
3 0x0 0xe8010000 0x00010000 // NAND CE2
>;
nor-boot@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0 0x0 0x4000000>;
bank-width = <2>;
partition@0 {
label = "Primary OS";
reg = <0x00000000 0x180000>;
};
partition@180000 {
label = "Secondary OS";
reg = <0x00180000 0x180000>;
};
partition@300000 {
label = "User";
reg = <0x00300000 0x3c80000>;
};
partition@3f80000 {
label = "Boot firmware";
reg = <0x03f80000 0x80000>;
};
};
nor-alternate@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <1 0x0 0x4000000>;
bank-width = <2>;
partition@0 {
label = "Filesystem";
reg = <0x00000000 0x3f80000>;
};
partition@3f80000 {
label = "Alternate boot firmware";
reg = <0x03f80000 0x80000>;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xes,address-ctl-nand";
reg = <2 0x0 0x10000>;
cle-line = <0x8>; /* CLE tied to A3 */
ale-line = <0x10>; /* ALE tied to A4 */
partition@0 {
label = "NAND Filesystem";
reg = <0 0x40000000>;
};
};
};
/* PMC interface */
pci0: pci@ef008000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
reg = <0xef008000 0x1000>;
clock-frequency = <33333333>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
};
/* XMC PCIe */
pci1: pcie@ef00a000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0x00000 0 0 1 &mpic 0 1
0x00000 0 0 2 &mpic 1 1
0x00000 0 0 3 &mpic 2 1
0x00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
bus-range = <0 0xff>;
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xef00a000 0x1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0 0xc0000000 0x02000000 0
0xc0000000 0 0x20000000
0x01000000 0 0x00000000 0x01000000 0
0x00000000 0 0x08000000>;
};
};
/* Needed for dtbImage boot wrapper compatibility */
chosen {
linux,stdout-path = &serial0;
};
};
arch/powerpc/boot/dts/xpedite5301.dts 0 → 100644
浏览文件 @ 773d7a09
/*
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
*
* XPedite5301 PMC/XMC module based on MPC8572E
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/ {
model = "xes,xpedite5301";
compatible = "xes,xpedite5301", "xes,MPC8572";
#address-cells = <2>;
#size-cells = <2>;
form-factor = "PMC/XMC";
boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8572@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
PowerPC,8572@1 {
device_type = "cpu";
reg = <0x1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
};
localbus@ef005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xef005000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
/* Local bus region mappings */
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
nor-boot@0,0 {
compatible = "amd,s29gl01gp", "cfi-flash";
bank-width = <2>;
reg = <0 0 0x8000000>; /* 128MB */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Primary user space";
reg = <0x00000000 0x6f00000>; /* 111 MB */
};
partition@6f00000 {
label = "Primary kernel";
reg = <0x6f00000 0x1000000>; /* 16 MB */
};
partition@7f00000 {
label = "Primary DTB";
reg = <0x7f00000 0x40000>; /* 256 KB */
};
partition@7f40000 {
label = "Primary U-Boot environment";
reg = <0x7f40000 0x40000>; /* 256 KB */
};
partition@7f80000 {
label = "Primary U-Boot";
reg = <0x7f80000 0x80000>; /* 512 KB */
read-only;
};
};
nor-alternate@1,0 {
compatible = "amd,s29gl01gp", "cfi-flash";
bank-width = <2>;
//reg = <0xf0000000 0x08000000>; /* 128MB */
reg = <1 0 0x8000000>; /* 128MB */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Secondary user space";
reg = <0x00000000 0x6f00000>; /* 111 MB */
};
partition@6f00000 {
label = "Secondary kernel";
reg = <0x6f00000 0x1000000>; /* 16 MB */
};
partition@7f00000 {
label = "Secondary DTB";
reg = <0x7f00000 0x40000>; /* 256 KB */
};
partition@7f40000 {
label = "Secondary U-Boot environment";
reg = <0x7f40000 0x40000>; /* 256 KB */
};
partition@7f80000 {
label = "Secondary U-Boot";
reg = <0x7f80000 0x80000>; /* 512 KB */
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
/*
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
* Micron MT29F8G08DAA (2x 512 MB), or Micron
* MT29F16G08FAA (2x 1 GB), depending on the build
* configuration
*/
compatible = "fsl,mpc8572-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <2 0 0x40000>;
/* U-Boot should fix this up if chip size > 1 GB */
partition@0 {
label = "NAND Filesystem";
reg = <0 0x40000000>;
};
};
};
soc8572@ef000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8572-immr", "simple-bus";
ranges = <0x0 0 0xef000000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x6000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x100000>; // L2, 1M
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
temp-sensor@48 {
compatible = "dallas,ds1631", "dallas,ds1621";
reg = <0x48>;
};
temp-sensor@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
cpu-supervisor@51 {
compatible = "dallas,ds4510";
reg = <0x51>;
};
eeprom@54 {
compatible = "atmel,at24c128b";
reg = <0x54>;
};
rtc@68 {
compatible = "stm,m41t00",
"dallas,ds1338";
reg = <0x68>;
};
pcie-switch@70 {
compatible = "plx,pex8518";
reg = <0x70>;
};
gpio1: gpio@18 {
compatible = "nxp,pca9557";
reg = <0x18>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
gpio2: gpio@1c {
compatible = "nxp,pca9557";
reg = <0x1c>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
gpio3: gpio@1e {
compatible = "nxp,pca9557";
reg = <0x1e>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
gpio4: gpio@1f {
compatible = "nxp,pca9557";
reg = <0x1f>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0xc300 0x4>;
ranges = <0x0 0xc100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
/* eTSEC 1 */
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x1>;
};
phy1: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x2>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC 2 */
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* UART0 */
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
/* UART1 */
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
msi@41600 {
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
crypto@30000 {
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
"fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x9fe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
gpio0: gpio@f000 {
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x1000>;
interrupts = <47 2>;
interrupt-parent = <&mpic>;
#gpio-cells = <2>;
gpio-controller;
};
gpio-leds {
compatible = "gpio-leds";
heartbeat {
label = "Heartbeat";
gpios = <&gpio0 4 1>;
linux,default-trigger = "heartbeat";
};
yellow {
label = "Yellow";
gpios = <&gpio0 5 1>;
};
red {
label = "Red";
gpios = <&gpio0 6 1>;
};
green {
label = "Green";
gpios = <&gpio0 7 1>;
};
};
/* PME (pattern-matcher) */
pme@10000 {
compatible = "fsl,mpc8572-pme", "pme8572";
reg = <0x10000 0x5000>;
interrupts = <57 2 64 2 65 2 66 2 67 2>;
interrupt-parent = <&mpic>;
};
tlu@2f000 {
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
reg = <0x2f000 0x1000>;
interupts = <61 2 >;
interrupt-parent = <&mpic>;
};
tlu@15000 {
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
reg = <0x15000 0x1000>;
interupts = <75 2>;
interrupt-parent = <&mpic>;
};
};
/*
* PCI Express controller 3 @ ef008000 is not used.
* This would have been pci0 on other mpc85xx platforms.
*/
/* PCI Express controller 2, wired to XMC P15 connector */
pci1: pcie@ef009000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xef009000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x10000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
/* PCI Express controller 1, wired to PEX8112 for PMC interface */
pci2: pcie@ef00a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xef00a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x40000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
arch/powerpc/boot/dts/xpedite5330.dts 0 → 100644
浏览文件 @ 773d7a09
/*
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
*
* XPedite5330 3U CompactPCI module based on MPC8572E
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/ {
model = "xes,xpedite5330";
compatible = "xes,xpedite5330", "xes,MPC8572";
#address-cells = <2>;
#size-cells = <2>;
form-factor = "3U CompactPCI";
boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
pmcslots {
#address-cells = <1>;
#size-cells = <0>;
pmcslot@0 {
cell-index = <0>;
/*
* boolean properties (true if defined):
* monarch;
* module-present;
*/
};
};
xmcslots {
#address-cells = <1>;
#size-cells = <0>;
xmcslot@0 {
cell-index = <0>;
/*
* boolean properties (true if defined):
* module-present;
*/
};
};
cpci {
/*
* boolean properties (true if defined):
* system-controller;
*/
system-controller;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8572@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
PowerPC,8572@1 {
device_type = "cpu";
reg = <0x1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
};
localbus@ef005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xef005000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
/* Local bus region mappings */
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
nor-boot@0,0 {
compatible = "amd,s29gl01gp", "cfi-flash";
bank-width = <2>;
reg = <0 0 0x8000000>; /* 128MB */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Primary user space";
reg = <0x00000000 0x6f00000>; /* 111 MB */
};
partition@6f00000 {
label = "Primary kernel";
reg = <0x6f00000 0x1000000>; /* 16 MB */
};
partition@7f00000 {
label = "Primary DTB";
reg = <0x7f00000 0x40000>; /* 256 KB */
};
partition@7f40000 {
label = "Primary U-Boot environment";
reg = <0x7f40000 0x40000>; /* 256 KB */
};
partition@7f80000 {
label = "Primary U-Boot";
reg = <0x7f80000 0x80000>; /* 512 KB */
read-only;
};
};
nor-alternate@1,0 {
compatible = "amd,s29gl01gp", "cfi-flash";
bank-width = <2>;
//reg = <0xf0000000 0x08000000>; /* 128MB */
reg = <1 0 0x8000000>; /* 128MB */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Secondary user space";
reg = <0x00000000 0x6f00000>; /* 111 MB */
};
partition@6f00000 {
label = "Secondary kernel";
reg = <0x6f00000 0x1000000>; /* 16 MB */
};
partition@7f00000 {
label = "Secondary DTB";
reg = <0x7f00000 0x40000>; /* 256 KB */
};
partition@7f40000 {
label = "Secondary U-Boot environment";
reg = <0x7f40000 0x40000>; /* 256 KB */
};
partition@7f80000 {
label = "Secondary U-Boot";
reg = <0x7f80000 0x80000>; /* 512 KB */
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
/*
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
* Micron MT29F8G08DAA (2x 512 MB), or Micron
* MT29F16G08FAA (2x 1 GB), depending on the build
* configuration
*/
compatible = "fsl,mpc8572-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <2 0 0x40000>;
/* U-Boot should fix this up if chip size > 1 GB */
partition@0 {
label = "NAND Filesystem";
reg = <0 0x40000000>;
};
};
};
soc8572@ef000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8572-immr", "simple-bus";
ranges = <0x0 0 0xef000000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x6000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x100000>; // L2, 1M
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
temp-sensor@48 {
compatible = "dallas,ds1631", "dallas,ds1621";
reg = <0x48>;
};
temp-sensor@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
cpu-supervisor@51 {
compatible = "dallas,ds4510";
reg = <0x51>;
};
eeprom@54 {
compatible = "atmel,at24c128b";
reg = <0x54>;
};
rtc@68 {
compatible = "stm,m41t00",
"dallas,ds1338";
reg = <0x68>;
};
pcie-switch@70 {
compatible = "plx,pex8518";
reg = <0x70>;
};
gpio1: gpio@18 {
compatible = "nxp,pca9557";
reg = <0x18>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
gpio2: gpio@1c {
compatible = "nxp,pca9557";
reg = <0x1c>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
gpio3: gpio@1e {
compatible = "nxp,pca9557";
reg = <0x1e>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
gpio4: gpio@1f {
compatible = "nxp,pca9557";
reg = <0x1f>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0xc300 0x4>;
ranges = <0x0 0xc100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
/* eTSEC 1 */
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x1>;
};
phy1: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x2>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC 2 */
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* UART0 */
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
/* UART1 */
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
msi@41600 {
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
crypto@30000 {
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
"fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x9fe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
gpio0: gpio@f000 {
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x1000>;
interrupts = <47 2>;
interrupt-parent = <&mpic>;
#gpio-cells = <2>;
gpio-controller;
};
gpio-leds {
compatible = "gpio-leds";
heartbeat {
label = "Heartbeat";
gpios = <&gpio0 4 1>;
linux,default-trigger = "heartbeat";
};
yellow {
label = "Yellow";
gpios = <&gpio0 5 1>;
};
red {
label = "Red";
gpios = <&gpio0 6 1>;
};
green {
label = "Green";
gpios = <&gpio0 7 1>;
};
};
/* PME (pattern-matcher) */
pme@10000 {
compatible = "fsl,mpc8572-pme", "pme8572";
reg = <0x10000 0x5000>;
interrupts = <57 2 64 2 65 2 66 2 67 2>;
interrupt-parent = <&mpic>;
};
tlu@2f000 {
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
reg = <0x2f000 0x1000>;
interupts = <61 2 >;
interrupt-parent = <&mpic>;
};
tlu@15000 {
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
reg = <0x15000 0x1000>;
interupts = <75 2>;
interrupt-parent = <&mpic>;
};
};
/* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
pci0: pcie@ef008000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xef008000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
interrupt-map = <
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0xe0000000
0x02000000 0x0 0xe0000000
0x0 0x10000000
0x01000000 0x0 0x0
0x01000000 0x0 0x0
0x0 0x100000>;
};
};
/* PCI Express controller 2, PMC module via PEX8112 bridge */
pci1: pcie@ef009000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xef009000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x10000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
/* PCI Express controller 1, XMC P15 */
pci2: pcie@ef00a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xef00a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x40000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
arch/powerpc/boot/dts/xpedite5370.dts 0 → 100644
浏览文件 @ 773d7a09
/*
* Copyright (C) 2008 Extreme Engineering Solutions, Inc.
* Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
*
* XPedite5370 3U VPX single-board computer based on MPC8572E
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/ {
model = "xes,xpedite5370";
compatible = "xes,xpedite5370", "xes,MPC8572";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8572@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
PowerPC,8572@1 {
device_type = "cpu";
reg = <0x1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
};
localbus@ef005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xef005000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
/* Local bus region mappings */
ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
nor-boot@0,0 {
compatible = "amd,s29gl01gp", "cfi-flash";
bank-width = <2>;
reg = <0 0 0x8000000>; /* 128MB */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Primary user space";
reg = <0x00000000 0x6f00000>; /* 111 MB */
};
partition@6f00000 {
label = "Primary kernel";
reg = <0x6f00000 0x1000000>; /* 16 MB */
};
partition@7f00000 {
label = "Primary DTB";
reg = <0x7f00000 0x40000>; /* 256 KB */
};
partition@7f40000 {
label = "Primary U-Boot environment";
reg = <0x7f40000 0x40000>; /* 256 KB */
};
partition@7f80000 {
label = "Primary U-Boot";
reg = <0x7f80000 0x80000>; /* 512 KB */
read-only;
};
};
nor-alternate@1,0 {
compatible = "amd,s29gl01gp", "cfi-flash";
bank-width = <2>;
//reg = <0xf0000000 0x08000000>; /* 128MB */
reg = <1 0 0x8000000>; /* 128MB */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Secondary user space";
reg = <0x00000000 0x6f00000>; /* 111 MB */
};
partition@6f00000 {
label = "Secondary kernel";
reg = <0x6f00000 0x1000000>; /* 16 MB */
};
partition@7f00000 {
label = "Secondary DTB";
reg = <0x7f00000 0x40000>; /* 256 KB */
};
partition@7f40000 {
label = "Secondary U-Boot environment";
reg = <0x7f40000 0x40000>; /* 256 KB */
};
partition@7f80000 {
label = "Secondary U-Boot";
reg = <0x7f80000 0x80000>; /* 512 KB */
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
/*
* Actual part could be ST Micro NAND08GW3B2A (1 GB),
* Micron MT29F8G08DAA (2x 512 MB), or Micron
* MT29F16G08FAA (2x 1 GB), depending on the build
* configuration
*/
compatible = "fsl,mpc8572-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <2 0 0x40000>;
/* U-Boot should fix this up if chip size > 1 GB */
partition@0 {
label = "NAND Filesystem";
reg = <0 0x40000000>;
};
};
};
soc8572@ef000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8572-immr", "simple-bus";
ranges = <0x0 0 0xef000000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x6000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x100000>; // L2, 1M
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
temp-sensor@48 {
compatible = "dallas,ds1631", "dallas,ds1621";
reg = <0x48>;
};
temp-sensor@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
cpu-supervisor@51 {
compatible = "dallas,ds4510";
reg = <0x51>;
};
eeprom@54 {
compatible = "atmel,at24c128b";
reg = <0x54>;
};
rtc@68 {
compatible = "stm,m41t00",
"dallas,ds1338";
reg = <0x68>;
};
pcie-switch@70 {
compatible = "plx,pex8518";
reg = <0x70>;
};
gpio1: gpio@18 {
compatible = "nxp,pca9557";
reg = <0x18>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
gpio2: gpio@1c {
compatible = "nxp,pca9557";
reg = <0x1c>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
gpio3: gpio@1e {
compatible = "nxp,pca9557";
reg = <0x1e>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
gpio4: gpio@1f {
compatible = "nxp,pca9557";
reg = <0x1f>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0xc300 0x4>;
ranges = <0x0 0xc100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
/* eTSEC 1 */
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x1>;
};
phy1: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x2>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC 2 */
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "sgmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* UART0 */
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
/* UART1 */
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
msi@41600 {
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
crypto@30000 {
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
"fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x9fe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
gpio0: gpio@f000 {
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x1000>;
interrupts = <47 2>;
interrupt-parent = <&mpic>;
#gpio-cells = <2>;
gpio-controller;
};
gpio-leds {
compatible = "gpio-leds";
heartbeat {
label = "Heartbeat";
gpios = <&gpio0 4 1>;
linux,default-trigger = "heartbeat";
};
yellow {
label = "Yellow";
gpios = <&gpio0 5 1>;
};
red {
label = "Red";
gpios = <&gpio0 6 1>;
};
green {
label = "Green";
gpios = <&gpio0 7 1>;
};
};
/* PME (pattern-matcher) */
pme@10000 {
compatible = "fsl,mpc8572-pme", "pme8572";
reg = <0x10000 0x5000>;
interrupts = <57 2 64 2 65 2 66 2 67 2>;
interrupt-parent = <&mpic>;
};
tlu@2f000 {
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
reg = <0x2f000 0x1000>;
interupts = <61 2 >;
interrupt-parent = <&mpic>;
};
tlu@15000 {
compatible = "fsl,mpc8572-tlu", "fsl_tlu";
reg = <0x15000 0x1000>;
interupts = <75 2>;
interrupt-parent = <&mpic>;
};
};
/*
* PCI Express controller 3 @ ef008000 is not used.
* This would have been pci0 on other mpc85xx platforms.
*/
/* PCI Express controller 2, wired to VPX P1,P2 backplane */
pci1: pcie@ef009000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xef009000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0 0x0 0x0 0x1 &mpic 0x4 0x1
0x0 0x0 0x0 0x2 &mpic 0x5 0x1
0x0 0x0 0x0 0x3 &mpic 0x6 0x1
0x0 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x10000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
/* PCI Express controller 1, wired to PEX8518 PCIe switch */
pci2: pcie@ef00a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xef00a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0x0 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x40000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
arch/powerpc/boot/wrapper
浏览文件 @ 773d7a09
......@@ -225,6 +225,10 @@ asp834x-redboot)
platformo="$object/fixed-head.o $object/redboot-83xx.o"
binary=y
;;
xpedite52*)
link_address='0x1400000'
platformo=$object/cuboot-85xx.o
;;
esac
vmz="$tmpdir/`basename \"$kernel\"`.$ext"
......
arch/powerpc/configs/83xx/kmeter1_defconfig 0 → 100644
浏览文件 @ 773d7a09
此差异已折叠。
arch/powerpc/configs/85xx/xes_mpc85xx_defconfig 0 → 100644
浏览文件 @ 773d7a09
此差异已折叠。
arch/powerpc/include/asm/delay.h
浏览文件 @ 773d7a09
......@@ -2,8 +2,11 @@
#define _ASM_POWERPC_DELAY_H
#ifdef __KERNEL__
#include <asm/time.h>
/*
* Copyright 1996, Paul Mackerras.
* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
......@@ -30,5 +33,38 @@ extern void udelay(unsigned long usecs);
#define mdelay(n) udelay((n) * 1000)
#endif
/**
* spin_event_timeout - spin until a condition gets true or a timeout elapses
* @condition: a C expression to evalate
* @timeout: timeout, in microseconds
* @delay: the number of microseconds to delay between each evaluation of
* @condition
*
* The process spins until the condition evaluates to true (non-zero) or the
* timeout elapses. The return value of this macro is the value of
* @condition when the loop terminates. This allows you to determine the cause
* of the loop terminates. If the return value is zero, then you know a
* timeout has occurred.
*
* This primary purpose of this macro is to poll on a hardware register
* until a status bit changes. The timeout ensures that the loop still
* terminates even if the bit never changes. The delay is for devices that
* need a delay in between successive reads.
*
* gcc will optimize out the if-statement if @delay is a constant.
*/
#define spin_event_timeout(condition, timeout, delay) \
({ \
typeof(condition) __ret; \
unsigned long __loops = tb_ticks_per_usec * timeout; \
unsigned long __start = get_tbl(); \
while (!(__ret = (condition)) && (tb_ticks_since(__start) <= __loops)) \
if (delay) \
udelay(delay); \
else \
cpu_relax(); \
__ret; \
})
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_DELAY_H */
arch/powerpc/include/asm/fsl_lbc.h
浏览文件 @ 773d7a09
......@@ -95,8 +95,8 @@ struct fsl_lbc_bank {
};
struct fsl_lbc_regs {
struct fsl_lbc_bank bank[8];
u8 res0[0x28];
struct fsl_lbc_bank bank[12];
u8 res0[0x8];
__be32 mar; /**< UPM Address Register */
u8 res1[0x4];
__be32 mamr; /**< UPMA Mode Register */
......
arch/powerpc/include/asm/mpc52xx.h
浏览文件 @ 773d7a09
......@@ -16,6 +16,7 @@
#ifndef __ASSEMBLY__
#include <asm/types.h>
#include <asm/prom.h>
#include <asm/mpc5xxx.h>
#endif /* __ASSEMBLY__ */
#include <linux/suspend.h>
......@@ -268,7 +269,6 @@ struct mpc52xx_intr {
#ifndef __ASSEMBLY__
/* mpc52xx_common.c */
extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
extern void mpc5200_setup_xlb_arbiter(void);
extern void mpc52xx_declare_of_platform_devices(void);
extern void mpc52xx_map_common_devices(void);
......
arch/powerpc/include/asm/mpc512x.h → arch/powerpc/include/asm/mpc5xxx.h
浏览文件 @ 773d7a09
......@@ -4,7 +4,7 @@
* Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007
*
* Description:
* MPC5121 Prototypes and definitions
* MPC5xxx Prototypes and definitions
*
* This is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by
......@@ -13,10 +13,10 @@
*
*/
#ifndef __ASM_POWERPC_MPC512x_H__
#define __ASM_POWERPC_MPC512x_H__
#ifndef __ASM_POWERPC_MPC5xxx_H__
#define __ASM_POWERPC_MPC5xxx_H__
extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
extern unsigned long mpc5xxx_get_bus_frequency(struct device_node *node);
#endif /* __ASM_POWERPC_MPC512x_H__ */
#endif /* __ASM_POWERPC_MPC5xxx_H__ */
arch/powerpc/include/asm/reg.h
浏览文件 @ 773d7a09
......@@ -755,7 +755,8 @@
#define mfspr(rn) ({unsigned long rval; \
asm volatile("mfspr %0," __stringify(rn) \
: "=r" (rval)); rval;})
#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)\
: "memory")
#ifdef __powerpc64__
#ifdef CONFIG_PPC_CELL
......
arch/powerpc/include/asm/reg_booke.h
浏览文件 @ 773d7a09
......@@ -389,12 +389,14 @@
#define ICCR_CACHE 1 /* Cacheable */
/* Bit definitions for L1CSR0. */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
/* Bit definitions for L1CSR1. */
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
......
arch/powerpc/kernel/Makefile
浏览文件 @ 773d7a09
......@@ -4,6 +4,8 @@
CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
ifeq ($(CONFIG_PPC64),y)
CFLAGS_prom_init.o += -mno-minimal-toc
endif
......
arch/powerpc/kernel/cpu_setup_6xx.S
浏览文件 @ 773d7a09
......@@ -239,6 +239,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
ori r11,r11,HID0_LRSTK | HID0_BTIC
oris r11,r11,HID0_DPM@h
BEGIN_MMU_FTR_SECTION
oris r11,r11,HID0_HIGH_BAT@h
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
BEGIN_FTR_SECTION
xori r11,r11,HID0_BTIC
END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
......
arch/powerpc/kernel/cpu_setup_fsl_booke.S
浏览文件 @ 773d7a09
......@@ -17,6 +17,40 @@
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
_GLOBAL(__e500_icache_setup)
mfspr r0, SPRN_L1CSR1
andi. r3, r0, L1CSR1_ICE
bnelr /* Already enabled */
oris r0, r0, L1CSR1_CPE@h
ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
isync
blr
_GLOBAL(__e500_dcache_setup)
mfspr r0, SPRN_L1CSR0
andi. r3, r0, L1CSR0_DCE
bnelr /* Already enabled */
msync
isync
li r0, 0
mtspr SPRN_L1CSR0, r0 /* Disable */
msync
isync
li r0, (L1CSR0_DCFI | L1CSR0_CLFC)
mtspr SPRN_L1CSR0, r0 /* Invalidate */
isync
1: mfspr r0, SPRN_L1CSR0
andi. r3, r0, L1CSR0_CLFC
bne+ 1b /* Wait for lock bits reset */
oris r0, r0, L1CSR0_CPE@h
ori r0, r0, L1CSR0_DCE
msync
isync
mtspr SPRN_L1CSR0, r0 /* Enable */
isync
blr
_GLOBAL(__setup_cpu_e200)
/* enable dedicated debug exception handling resources (Debug APU) */
mfspr r3,SPRN_HID0
......@@ -25,7 +59,16 @@ _GLOBAL(__setup_cpu_e200)
b __setup_e200_ivors
_GLOBAL(__setup_cpu_e500v1)
_GLOBAL(__setup_cpu_e500v2)
b __setup_e500_ivors
mflr r4
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
mtlr r4
blr
_GLOBAL(__setup_cpu_e500mc)
b __setup_e500mc_ivors
mflr r4
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500mc_ivors
mtlr r4
blr
arch/powerpc/kvm/Makefile
浏览文件 @ 773d7a09
......@@ -2,6 +2,8 @@
# Makefile for Kernel-based Virtual Machine module
#
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
EXTRA_CFLAGS += -Ivirt/kvm -Iarch/powerpc/kvm
common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
......
arch/powerpc/lib/Makefile
浏览文件 @ 773d7a09
......@@ -2,6 +2,8 @@
# Makefile for ppc-specific library files..
#
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
ifeq ($(CONFIG_PPC64),y)
EXTRA_CFLAGS += -mno-minimal-toc
endif
......
arch/powerpc/mm/Makefile
浏览文件 @ 773d7a09
......@@ -2,6 +2,8 @@
# Makefile for the linux ppc-specific parts of the memory manager.
#
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
ifeq ($(CONFIG_PPC64),y)
EXTRA_CFLAGS += -mno-minimal-toc
endif
......
arch/powerpc/oprofile/Makefile
浏览文件 @ 773d7a09
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
ifeq ($(CONFIG_PPC64),y)
EXTRA_CFLAGS += -mno-minimal-toc
endif
......
arch/powerpc/platforms/44x/warp.c
浏览文件 @ 773d7a09
......@@ -43,7 +43,13 @@ static int __init warp_probe(void)
{
unsigned long root = of_get_flat_dt_root();
return of_flat_dt_is_compatible(root, "pika,warp");
if (!of_flat_dt_is_compatible(root, "pika,warp"))
return 0;
/* For __dma_alloc_coherent */
ISA_DMA_THRESHOLD = ~0L;
return 1;
}
define_machine(warp) {
......
arch/powerpc/platforms/512x/clock.c
浏览文件 @ 773d7a09
......@@ -24,7 +24,7 @@
#include <linux/io.h>
#include <linux/of_platform.h>
#include <asm/mpc512x.h>
#include <asm/mpc5xxx.h>
#include <asm/clk_interface.h>
#undef CLK_DEBUG
......@@ -83,13 +83,13 @@ static void dump_clocks(void)
mutex_lock(&clocks_mutex);
printk(KERN_INFO "CLOCKS:\n");
list_for_each_entry(p, &clocks, node) {
printk(KERN_INFO " %s %ld", p->name, p->rate);
pr_info(" %s=%ld", p->name, p->rate);
if (p->parent)
printk(KERN_INFO " %s %ld", p->parent->name,
pr_cont(" %s=%ld", p->parent->name,
p->parent->rate);
if (p->flags & CLK_HAS_CTRL)
printk(KERN_INFO " reg/bit %d/%d", p->reg, p->bit);
printk("\n");
pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
pr_cont("\n");
}
mutex_unlock(&clocks_mutex);
}
......
arch/powerpc/platforms/512x/mpc512x.h
浏览文件 @ 773d7a09
......@@ -11,7 +11,6 @@
#ifndef __MPC512X_H__
#define __MPC512X_H__
extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
extern void __init mpc512x_init_IRQ(void);
void __init mpc512x_declare_of_platform_devices(void);
#endif /* __MPC512X_H__ */
arch/powerpc/platforms/512x/mpc512x_shared.c
浏览文件 @ 773d7a09
......@@ -24,29 +24,6 @@
#include "mpc512x.h"
unsigned long
mpc512x_find_ips_freq(struct device_node *node)
{
struct device_node *np;
const unsigned int *p_ips_freq = NULL;
of_node_get(node);
while (node) {
p_ips_freq = of_get_property(node, "bus-frequency", NULL);
if (p_ips_freq)
break;
np = of_get_parent(node);
of_node_put(node);
node = np;
}
if (node)
of_node_put(node);
return p_ips_freq ? *p_ips_freq : 0;
}
EXPORT_SYMBOL(mpc512x_find_ips_freq);
void __init mpc512x_init_IRQ(void)
{
struct device_node *np;
......
arch/powerpc/platforms/52xx/mpc52xx_common.c
浏览文件 @ 773d7a09
......@@ -47,36 +47,6 @@ static DEFINE_SPINLOCK(mpc52xx_lock);
static struct mpc52xx_gpt __iomem *mpc52xx_wdt;
static struct mpc52xx_cdm __iomem *mpc52xx_cdm;
/**
* mpc52xx_find_ipb_freq - Find the IPB bus frequency for a device
* @node: device node
*
* Returns IPB bus frequency, or 0 if the bus frequency cannot be found.
*/
unsigned int
mpc52xx_find_ipb_freq(struct device_node *node)
{
struct device_node *np;
const unsigned int *p_ipb_freq = NULL;
of_node_get(node);
while (node) {
p_ipb_freq = of_get_property(node, "bus-frequency", NULL);
if (p_ipb_freq)
break;
np = of_get_parent(node);
of_node_put(node);
node = np;
}
if (node)
of_node_put(node);
return p_ipb_freq ? *p_ipb_freq : 0;
}
EXPORT_SYMBOL(mpc52xx_find_ipb_freq);
/*
* Configure the XLB arbiter settings to match what Linux expects.
*/
......@@ -221,7 +191,7 @@ unsigned int mpc52xx_get_xtal_freq(struct device_node *node)
if (!mpc52xx_cdm)
return 0;
freq = mpc52xx_find_ipb_freq(node);
freq = mpc5xxx_get_bus_frequency(node);
if (!freq)
return 0;
......
arch/powerpc/platforms/83xx/Kconfig
浏览文件 @ 773d7a09
......@@ -96,6 +96,13 @@ config ASP834x
This enables support for the Analogue & Micro ASP 83xx
board.
config KMETER1
bool "Keymile KMETER1"
select DEFAULT_UIMAGE
select QUICC_ENGINE
help
This enables support for the Keymile KMETER1 board.
endif
......
arch/powerpc/platforms/83xx/Makefile
浏览文件 @ 773d7a09
......@@ -15,3 +15,4 @@ obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o
obj-$(CONFIG_SBC834x) += sbc834x.o
obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o
obj-$(CONFIG_ASP834x) += asp834x.o
obj-$(CONFIG_KMETER1) += kmeter1.o
arch/powerpc/platforms/83xx/kmeter1.c 0 → 100644
浏览文件 @ 773d7a09
此差异已折叠。
arch/powerpc/platforms/83xx/mpc83xx.h
浏览文件 @ 773d7a09
......@@ -22,8 +22,8 @@
/* system i/o configuration register low */
#define MPC83XX_SICRL_OFFS 0x114
#define MPC834X_SICRL_USB_MASK 0x60000000
#define MPC834X_SICRL_USB0 0x40000000
#define MPC834X_SICRL_USB1 0x20000000
#define MPC834X_SICRL_USB0 0x20000000
#define MPC834X_SICRL_USB1 0x40000000
#define MPC831X_SICRL_USB_MASK 0x00000c00
#define MPC831X_SICRL_USB_ULPI 0x00000800
#define MPC8315_SICRL_USB_MASK 0x000000fc
......
arch/powerpc/platforms/83xx/usb.c
浏览文件 @ 773d7a09
......@@ -47,25 +47,25 @@ int mpc834x_usb_cfg(void)
sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */
prop = of_get_property(np, "phy_type", NULL);
port1_is_dr = 1;
if (prop && (!strcmp(prop, "utmi") ||
!strcmp(prop, "utmi_wide"))) {
sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
sicrh |= MPC834X_SICRH_USB_UTMI;
port1_is_dr = 1;
port0_is_dr = 1;
} else if (prop && !strcmp(prop, "serial")) {
dr_mode = of_get_property(np, "dr_mode", NULL);
if (dr_mode && !strcmp(dr_mode, "otg")) {
sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
port1_is_dr = 1;
port0_is_dr = 1;
} else {
sicrl |= MPC834X_SICRL_USB0;
sicrl |= MPC834X_SICRL_USB1;
}
} else if (prop && !strcmp(prop, "ulpi")) {
sicrl |= MPC834X_SICRL_USB0;
sicrl |= MPC834X_SICRL_USB1;
} else {
printk(KERN_WARNING "834x USB PHY type not supported\n");
}
port0_is_dr = 1;
of_node_put(np);
}
np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph");
......
arch/powerpc/platforms/85xx/Kconfig
浏览文件 @ 773d7a09
......@@ -35,12 +35,14 @@ config MPC85xx_MDS
select DEFAULT_UIMAGE
select PHYLIB
select HAS_RAPIDIO
select SWIOTLB
help
This option enables support for the MPC85xx MDS board
config MPC8536_DS
bool "Freescale MPC8536 DS"
select DEFAULT_UIMAGE
select SWIOTLB
help
This option enables support for the MPC8536 DS board
......@@ -49,6 +51,7 @@ config MPC85xx_DS
select PPC_I8259
select DEFAULT_UIMAGE
select FSL_ULI1575
select SWIOTLB
help
This option enables support for the MPC85xx DS (MPC8544 DS) board
......@@ -64,6 +67,16 @@ config KSI8560
help
This option enables support for the Emerson KSI8560 board
config XES_MPC85xx
bool "X-ES single-board computer"
select DEFAULT_UIMAGE
help
This option enables support for the various single-board
computers from Extreme Engineering Solutions (X-ES) based on
Freescale MPC85xx processors.
Manufacturer: Extreme Engineering Solutions, Inc.
URL: <http://www.xes-inc.com/>
config STX_GP3
bool "Silicon Turnkey Express GP3"
help
......
arch/powerpc/platforms/85xx/Makefile
浏览文件 @ 773d7a09
......@@ -15,3 +15,4 @@ obj-$(CONFIG_SBC8560) += sbc8560.o
obj-$(CONFIG_SBC8548) += sbc8548.o
obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
obj-$(CONFIG_KSI8560) += ksi8560.o
obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
\ No newline at end of file
arch/powerpc/platforms/85xx/xes_mpc85xx.c 0 → 100644
浏览文件 @ 773d7a09
此差异已折叠。
arch/powerpc/platforms/86xx/Kconfig
浏览文件 @ 773d7a09
......@@ -15,6 +15,7 @@ config MPC8641_HPCN
select DEFAULT_UIMAGE
select FSL_ULI1575
select HAS_RAPIDIO
select SWIOTLB
help
This option enables support for the MPC8641 HPCN board.
......
arch/powerpc/platforms/Makefile
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此差异已折叠。
arch/powerpc/sysdev/Makefile
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此差异已折叠。
arch/powerpc/sysdev/mpc5xxx_clocks.c 0 → 100644
浏览文件 @ 773d7a09
此差异已折叠。
arch/powerpc/xmon/Makefile
浏览文件 @ 773d7a09
此差异已折叠。
drivers/ata/pata_mpc52xx.c
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此差异已折叠。
drivers/char/hvc_iseries.c
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此差异已折叠。
drivers/char/hvc_vio.c
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此差异已折叠。
drivers/char/hvcs.c
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此差异已折叠。
drivers/i2c/busses/i2c-mpc.c
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此差异已折叠。
drivers/net/fec_mpc52xx.c
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此差异已折叠。
drivers/net/fec_mpc52xx_phy.c
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此差异已折叠。
drivers/net/ps3_gelic_net.c
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此差异已折叠。
drivers/net/ps3_gelic_wireless.c
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此差异已折叠。
drivers/rapidio/rio-scan.c
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此差异已折叠。
drivers/rapidio/rio-sysfs.c
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此差异已折叠。
drivers/scsi/ps3rom.c
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此差异已折叠。
drivers/serial/mpc52xx_uart.c
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此差异已折叠。
drivers/serial/of_serial.c
浏览文件 @ 773d7a09
此差异已折叠。
drivers/serial/ucc_uart.c
浏览文件 @ 773d7a09
此差异已折叠。
drivers/usb/host/ehci-ps3.c
浏览文件 @ 773d7a09
此差异已折叠。
drivers/usb/host/ohci-ps3.c
浏览文件 @ 773d7a09
此差异已折叠。
drivers/video/xilinxfb.c
浏览文件 @ 773d7a09
此差异已折叠。
drivers/watchdog/mpc5200_wdt.c
浏览文件 @ 773d7a09
此差异已折叠。
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