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kernel_linux
提交 6eafa460 编写于 作者: G Greg Kroah-Hartman
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Merge 3.1-rc4 into staging-next 

This resolves a conflict with:
	drivers/staging/brcm80211/brcmsmac/types.h
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 c6a389f1 b9c4decb
展开全部 隐藏空白更改
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Showing with 99186 addition and 106629 deletion
arch/x86/include/asm/hyperv.h
浏览文件 @ 6eafa460
......@@ -189,5 +189,6 @@
#define HV_STATUS_INVALID_HYPERCALL_CODE 2
#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
#define HV_STATUS_INVALID_ALIGNMENT 4
#define HV_STATUS_INSUFFICIENT_BUFFERS 19
#endif
drivers/char/scc.h 已删除 100644 → 0
浏览文件 @ c6a389f1
/*
* atari_SCC.h: Definitions for the Am8530 Serial Communications Controller
*
* Copyright 1994 Roman Hodek <Roman.Hodek@informatik.uni-erlangen.de>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
*/
#ifndef _SCC_H
#define _SCC_H
#include <linux/delay.h>
/* Special configuration ioctls for the Atari SCC5380 Serial
* Communications Controller
*/
/* ioctl command codes */
#define TIOCGATSCC 0x54c0 /* get SCC configuration */
#define TIOCSATSCC 0x54c1 /* set SCC configuration */
#define TIOCDATSCC 0x54c2 /* reset configuration to defaults */
/* Clock sources */
#define CLK_RTxC 0
#define CLK_TRxC 1
#define CLK_PCLK 2
/* baud_bases for the common clocks in the Atari. These are the real
* frequencies divided by 16.
*/
#define SCC_BAUD_BASE_TIMC 19200 /* 0.3072 MHz from TT-MFP, Timer C */
#define SCC_BAUD_BASE_BCLK 153600 /* 2.4576 MHz */
#define SCC_BAUD_BASE_PCLK4 229500 /* 3.6720 MHz */
#define SCC_BAUD_BASE_PCLK 503374 /* 8.0539763 MHz */
#define SCC_BAUD_BASE_NONE 0 /* for not connected or unused
* clock sources */
/* The SCC clock configuration structure */
struct scc_clock_config {
unsigned RTxC_base; /* base_baud of RTxC */
unsigned TRxC_base; /* base_baud of TRxC */
unsigned PCLK_base; /* base_baud of PCLK, both channels! */
struct {
unsigned clksrc; /* CLK_RTxC, CLK_TRxC or CLK_PCLK */
unsigned divisor; /* divisor for base baud, valid values:
* see below */
} baud_table[17]; /* For 50, 75, 110, 135, 150, 200, 300,
* 600, 1200, 1800, 2400, 4800, 9600,
* 19200, 38400, 57600 and 115200 bps.
* The last two could be replaced by
* other rates > 38400 if they're not
* possible.
*/
};
/* The following divisors are valid:
*
* - CLK_RTxC: 1 or even (1, 2 and 4 are the direct modes, > 4 use
* the BRG)
*
* - CLK_TRxC: 1, 2 or 4 (no BRG, only direct modes possible)
*
* - CLK_PCLK: >= 4 and even (no direct modes, only BRG)
*
*/
struct scc_port {
struct gs_port gs;
volatile unsigned char *ctrlp;
volatile unsigned char *datap;
int x_char; /* xon/xoff character */
int c_dcd;
int channel;
struct scc_port *port_a; /* Reference to port A and B */
struct scc_port *port_b; /* structs for reg access */
};
#define SCC_MAGIC 0x52696368
/***********************************************************************/
/* */
/* Register Names */
/* */
/***********************************************************************/
/* The SCC documentation gives no explicit names to the registers,
* they're just called WR0..15 and RR0..15. To make the source code
* better readable and make the transparent write reg read access (see
* below) possible, I christen them here with self-invented names.
* Note that (real) read registers are assigned numbers 16..31. WR7'
* has number 33.
*/
#define COMMAND_REG 0 /* wo */
#define INT_AND_DMA_REG 1 /* wo */
#define INT_VECTOR_REG 2 /* rw, common to both channels */
#define RX_CTRL_REG 3 /* rw */
#define AUX1_CTRL_REG 4 /* rw */
#define TX_CTRL_REG 5 /* rw */
#define SYNC_ADR_REG 6 /* wo */
#define SYNC_CHAR_REG 7 /* wo */
#define SDLC_OPTION_REG 33 /* wo */
#define TX_DATA_REG 8 /* wo */
#define MASTER_INT_CTRL 9 /* wo, common to both channels */
#define AUX2_CTRL_REG 10 /* rw */
#define CLK_CTRL_REG 11 /* wo */
#define TIMER_LOW_REG 12 /* rw */
#define TIMER_HIGH_REG 13 /* rw */
#define DPLL_CTRL_REG 14 /* wo */
#define INT_CTRL_REG 15 /* rw */
#define STATUS_REG 16 /* ro */
#define SPCOND_STATUS_REG 17 /* wo */
/* RR2 is WR2 for Channel A, Channel B gives vector + current status: */
#define CURR_VECTOR_REG 18 /* Ch. B only, Ch. A for rw */
#define INT_PENDING_REG 19 /* Channel A only! */
/* RR4 is WR4, if b6(MR7') == 1 */
/* RR5 is WR5, if b6(MR7') == 1 */
#define FS_FIFO_LOW_REG 22 /* ro */
#define FS_FIFO_HIGH_REG 23 /* ro */
#define RX_DATA_REG 24 /* ro */
/* RR9 is WR3, if b6(MR7') == 1 */
#define DPLL_STATUS_REG 26 /* ro */
/* RR11 is WR10, if b6(MR7') == 1 */
/* RR12 is WR12 */
/* RR13 is WR13 */
/* RR14 not present */
/* RR15 is WR15 */
/***********************************************************************/
/* */
/* Register Values */
/* */
/***********************************************************************/
/* WR0: COMMAND_REG "CR" */
#define CR_RX_CRC_RESET 0x40
#define CR_TX_CRC_RESET 0x80
#define CR_TX_UNDERRUN_RESET 0xc0
#define CR_EXTSTAT_RESET 0x10
#define CR_SEND_ABORT 0x18
#define CR_ENAB_INT_NEXT_RX 0x20
#define CR_TX_PENDING_RESET 0x28
#define CR_ERROR_RESET 0x30
#define CR_HIGHEST_IUS_RESET 0x38
/* WR1: INT_AND_DMA_REG "IDR" */
#define IDR_EXTSTAT_INT_ENAB 0x01
#define IDR_TX_INT_ENAB 0x02
#define IDR_PARERR_AS_SPCOND 0x04
#define IDR_RX_INT_DISAB 0x00
#define IDR_RX_INT_FIRST 0x08
#define IDR_RX_INT_ALL 0x10
#define IDR_RX_INT_SPCOND 0x18
#define IDR_RX_INT_MASK 0x18
#define IDR_WAITREQ_RX 0x20
#define IDR_WAITREQ_IS_REQ 0x40
#define IDR_WAITREQ_ENAB 0x80
/* WR3: RX_CTRL_REG "RCR" */
#define RCR_RX_ENAB 0x01
#define RCR_DISCARD_SYNC_CHARS 0x02
#define RCR_ADDR_SEARCH 0x04
#define RCR_CRC_ENAB 0x08
#define RCR_SEARCH_MODE 0x10
#define RCR_AUTO_ENAB_MODE 0x20
#define RCR_CHSIZE_MASK 0xc0
#define RCR_CHSIZE_5 0x00
#define RCR_CHSIZE_6 0x40
#define RCR_CHSIZE_7 0x80
#define RCR_CHSIZE_8 0xc0
/* WR4: AUX1_CTRL_REG "A1CR" */
#define A1CR_PARITY_MASK 0x03
#define A1CR_PARITY_NONE 0x00
#define A1CR_PARITY_ODD 0x01
#define A1CR_PARITY_EVEN 0x03
#define A1CR_MODE_MASK 0x0c
#define A1CR_MODE_SYNCR 0x00
#define A1CR_MODE_ASYNC_1 0x04
#define A1CR_MODE_ASYNC_15 0x08
#define A1CR_MODE_ASYNC_2 0x0c
#define A1CR_SYNCR_MODE_MASK 0x30
#define A1CR_SYNCR_MONOSYNC 0x00
#define A1CR_SYNCR_BISYNC 0x10
#define A1CR_SYNCR_SDLC 0x20
#define A1CR_SYNCR_EXTCSYNC 0x30
#define A1CR_CLKMODE_MASK 0xc0
#define A1CR_CLKMODE_x1 0x00
#define A1CR_CLKMODE_x16 0x40
#define A1CR_CLKMODE_x32 0x80
#define A1CR_CLKMODE_x64 0xc0
/* WR5: TX_CTRL_REG "TCR" */
#define TCR_TX_CRC_ENAB 0x01
#define TCR_RTS 0x02
#define TCR_USE_CRC_CCITT 0x00
#define TCR_USE_CRC_16 0x04
#define TCR_TX_ENAB 0x08
#define TCR_SEND_BREAK 0x10
#define TCR_CHSIZE_MASK 0x60
#define TCR_CHSIZE_5 0x00
#define TCR_CHSIZE_6 0x20
#define TCR_CHSIZE_7 0x40
#define TCR_CHSIZE_8 0x60
#define TCR_DTR 0x80
/* WR7': SLDC_OPTION_REG "SOR" */
#define SOR_AUTO_TX_ENAB 0x01
#define SOR_AUTO_EOM_RESET 0x02
#define SOR_AUTO_RTS_MODE 0x04
#define SOR_NRZI_DISAB_HIGH 0x08
#define SOR_ALT_DTRREQ_TIMING 0x10
#define SOR_READ_CRC_CHARS 0x20
#define SOR_EXTENDED_REG_ACCESS 0x40
/* WR9: MASTER_INT_CTRL "MIC" */
#define MIC_VEC_INCL_STAT 0x01
#define MIC_NO_VECTOR 0x02
#define MIC_DISAB_LOWER_CHAIN 0x04
#define MIC_MASTER_INT_ENAB 0x08
#define MIC_STATUS_HIGH 0x10
#define MIC_IGN_INTACK 0x20
#define MIC_NO_RESET 0x00
#define MIC_CH_A_RESET 0x40
#define MIC_CH_B_RESET 0x80
#define MIC_HARD_RESET 0xc0
/* WR10: AUX2_CTRL_REG "A2CR" */
#define A2CR_SYNC_6 0x01
#define A2CR_LOOP_MODE 0x02
#define A2CR_ABORT_ON_UNDERRUN 0x04
#define A2CR_MARK_IDLE 0x08
#define A2CR_GO_ACTIVE_ON_POLL 0x10
#define A2CR_CODING_MASK 0x60
#define A2CR_CODING_NRZ 0x00
#define A2CR_CODING_NRZI 0x20
#define A2CR_CODING_FM1 0x40
#define A2CR_CODING_FM0 0x60
#define A2CR_PRESET_CRC_1 0x80
/* WR11: CLK_CTRL_REG "CCR" */
#define CCR_TRxCOUT_MASK 0x03
#define CCR_TRxCOUT_XTAL 0x00
#define CCR_TRxCOUT_TXCLK 0x01
#define CCR_TRxCOUT_BRG 0x02
#define CCR_TRxCOUT_DPLL 0x03
#define CCR_TRxC_OUTPUT 0x04
#define CCR_TXCLK_MASK 0x18
#define CCR_TXCLK_RTxC 0x00
#define CCR_TXCLK_TRxC 0x08
#define CCR_TXCLK_BRG 0x10
#define CCR_TXCLK_DPLL 0x18
#define CCR_RXCLK_MASK 0x60
#define CCR_RXCLK_RTxC 0x00
#define CCR_RXCLK_TRxC 0x20
#define CCR_RXCLK_BRG 0x40
#define CCR_RXCLK_DPLL 0x60
#define CCR_RTxC_XTAL 0x80
/* WR14: DPLL_CTRL_REG "DCR" */
#define DCR_BRG_ENAB 0x01
#define DCR_BRG_USE_PCLK 0x02
#define DCR_DTRREQ_IS_REQ 0x04
#define DCR_AUTO_ECHO 0x08
#define DCR_LOCAL_LOOPBACK 0x10
#define DCR_DPLL_EDGE_SEARCH 0x20
#define DCR_DPLL_ERR_RESET 0x40
#define DCR_DPLL_DISAB 0x60
#define DCR_DPLL_CLK_BRG 0x80
#define DCR_DPLL_CLK_RTxC 0xa0
#define DCR_DPLL_FM 0xc0
#define DCR_DPLL_NRZI 0xe0
/* WR15: INT_CTRL_REG "ICR" */
#define ICR_OPTIONREG_SELECT 0x01
#define ICR_ENAB_BRG_ZERO_INT 0x02
#define ICR_USE_FS_FIFO 0x04
#define ICR_ENAB_DCD_INT 0x08
#define ICR_ENAB_SYNC_INT 0x10
#define ICR_ENAB_CTS_INT 0x20
#define ICR_ENAB_UNDERRUN_INT 0x40
#define ICR_ENAB_BREAK_INT 0x80
/* RR0: STATUS_REG "SR" */
#define SR_CHAR_AVAIL 0x01
#define SR_BRG_ZERO 0x02
#define SR_TX_BUF_EMPTY 0x04
#define SR_DCD 0x08
#define SR_SYNC_ABORT 0x10
#define SR_CTS 0x20
#define SR_TX_UNDERRUN 0x40
#define SR_BREAK 0x80
/* RR1: SPCOND_STATUS_REG "SCSR" */
#define SCSR_ALL_SENT 0x01
#define SCSR_RESIDUAL_MASK 0x0e
#define SCSR_PARITY_ERR 0x10
#define SCSR_RX_OVERRUN 0x20
#define SCSR_CRC_FRAME_ERR 0x40
#define SCSR_END_OF_FRAME 0x80
/* RR3: INT_PENDING_REG "IPR" */
#define IPR_B_EXTSTAT 0x01
#define IPR_B_TX 0x02
#define IPR_B_RX 0x04
#define IPR_A_EXTSTAT 0x08
#define IPR_A_TX 0x10
#define IPR_A_RX 0x20
/* RR7: FS_FIFO_HIGH_REG "FFHR" */
#define FFHR_CNT_MASK 0x3f
#define FFHR_IS_FROM_FIFO 0x40
#define FFHR_FIFO_OVERRUN 0x80
/* RR10: DPLL_STATUS_REG "DSR" */
#define DSR_ON_LOOP 0x02
#define DSR_ON_LOOP_SENDING 0x10
#define DSR_TWO_CLK_MISSING 0x40
#define DSR_ONE_CLK_MISSING 0x80
/***********************************************************************/
/* */
/* Register Access */
/* */
/***********************************************************************/
/* The SCC needs 3.5 PCLK cycles recovery time between to register
* accesses. PCLK runs with 8 MHz on an Atari, so this delay is 3.5 *
* 125 ns = 437.5 ns. This is too short for udelay().
* 10/16/95: A tstb st_mfp.par_dt_reg takes 600ns (sure?) and thus should be
* quite right
*/
#define scc_reg_delay() \
do { \
if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147) \
__asm__ __volatile__ ( " nop; nop"); \
else if (MACH_IS_ATARI) \
__asm__ __volatile__ ( "tstb %0" : : "g" (*_scc_del) : "cc" );\
} while (0)
static unsigned char scc_shadow[2][16];
/* The following functions should relax the somehow complicated
* register access of the SCC. _SCCwrite() stores all written values
* (except for WR0 and WR8) in shadow registers for later recall. This
* removes the burden of remembering written values as needed. The
* extra work of storing the value doesn't count, since a delay is
* needed after a SCC access anyway. Additionally, _SCCwrite() manages
* writes to WR0 and WR8 differently, because these can be accessed
* directly with less overhead. Another special case are WR7 and WR7'.
* _SCCwrite automatically checks what of this registers is selected
* and changes b0 of WR15 if needed.
*
* _SCCread() for standard read registers is straightforward, except
* for RR2 (split into two "virtual" registers: one for the value
* written to WR2 (from the shadow) and one for the vector including
* status from RR2, Ch. B) and RR3. The latter must be read from
* Channel A, because it reads as all zeros on Ch. B. RR0 and RR8 can
* be accessed directly as before.
*
* The two inline function contain complicated switch statements. But
* I rely on regno and final_delay being constants, so gcc can reduce
* the whole stuff to just some assembler statements.
*
* _SCCwrite and _SCCread aren't intended to be used directly under
* normal circumstances. The macros SCCread[_ND] and SCCwrite[_ND] are
* for that purpose. They assume that a local variable 'port' is
* declared and pointing to the port's scc_struct entry. The
* variants with "_NB" appended should be used if no other SCC
* accesses follow immediately (within 0.5 usecs). They just skip the
* final delay nops.
*
* Please note that accesses to SCC registers should only take place
* when interrupts are turned off (at least if SCC interrupts are
* enabled). Otherwise, an interrupt could interfere with the
* two-stage accessing process.
*
*/
static __inline__ void _SCCwrite(
struct scc_port *port,
unsigned char *shadow,
volatile unsigned char *_scc_del,
int regno,
unsigned char val, int final_delay )
{
switch( regno ) {
case COMMAND_REG:
/* WR0 can be written directly without pointing */
*port->ctrlp = val;
break;
case SYNC_CHAR_REG:
/* For WR7, first set b0 of WR15 to 0, if needed */
if (shadow[INT_CTRL_REG] & ICR_OPTIONREG_SELECT) {
*port->ctrlp = 15;
shadow[INT_CTRL_REG] &= ~ICR_OPTIONREG_SELECT;
scc_reg_delay();
*port->ctrlp = shadow[INT_CTRL_REG];
scc_reg_delay();
}
goto normal_case;
case SDLC_OPTION_REG:
/* For WR7', first set b0 of WR15 to 1, if needed */
if (!(shadow[INT_CTRL_REG] & ICR_OPTIONREG_SELECT)) {
*port->ctrlp = 15;
shadow[INT_CTRL_REG] |= ICR_OPTIONREG_SELECT;
scc_reg_delay();
*port->ctrlp = shadow[INT_CTRL_REG];
scc_reg_delay();
}
*port->ctrlp = 7;
shadow[8] = val; /* WR7' shadowed at WR8 */
scc_reg_delay();
*port->ctrlp = val;
break;
case TX_DATA_REG: /* WR8 */
/* TX_DATA_REG can be accessed directly on some h/w */
if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147)
{
*port->ctrlp = regno;
scc_reg_delay();
*port->ctrlp = val;
}
else
*port->datap = val;
break;
case MASTER_INT_CTRL:
*port->ctrlp = regno;
val &= 0x3f; /* bits 6..7 are the reset commands */
scc_shadow[0][regno] = val;
scc_reg_delay();
*port->ctrlp = val;
break;
case DPLL_CTRL_REG:
*port->ctrlp = regno;
val &= 0x1f; /* bits 5..7 are the DPLL commands */
shadow[regno] = val;
scc_reg_delay();
*port->ctrlp = val;
break;
case 1 ... 6:
case 10 ... 13:
case 15:
normal_case:
*port->ctrlp = regno;
shadow[regno] = val;
scc_reg_delay();
*port->ctrlp = val;
break;
default:
printk( "Bad SCC write access to WR%d\n", regno );
break;
}
if (final_delay)
scc_reg_delay();
}
static __inline__ unsigned char _SCCread(
struct scc_port *port,
unsigned char *shadow,
volatile unsigned char *_scc_del,
int regno, int final_delay )
{
unsigned char rv;
switch( regno ) {
/* --- real read registers --- */
case STATUS_REG:
rv = *port->ctrlp;
break;
case INT_PENDING_REG:
/* RR3: read only from Channel A! */
port = port->port_a;
goto normal_case;
case RX_DATA_REG:
/* RR8 can be accessed directly on some h/w */
if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147)
{
*port->ctrlp = 8;
scc_reg_delay();
rv = *port->ctrlp;
}
else
rv = *port->datap;
break;
case CURR_VECTOR_REG:
/* RR2 (vector including status) from Ch. B */
port = port->port_b;
goto normal_case;
/* --- reading write registers: access the shadow --- */
case 1 ... 7:
case 10 ... 15:
return shadow[regno]; /* no final delay! */
/* WR7' is special, because it is shadowed at the place of WR8 */
case SDLC_OPTION_REG:
return shadow[8]; /* no final delay! */
/* WR9 is special too, because it is common for both channels */
case MASTER_INT_CTRL:
return scc_shadow[0][9]; /* no final delay! */
default:
printk( "Bad SCC read access to %cR%d\n", (regno & 16) ? 'R' : 'W',
regno & ~16 );
break;
case SPCOND_STATUS_REG:
case FS_FIFO_LOW_REG:
case FS_FIFO_HIGH_REG:
case DPLL_STATUS_REG:
normal_case:
*port->ctrlp = regno & 0x0f;
scc_reg_delay();
rv = *port->ctrlp;
break;
}
if (final_delay)
scc_reg_delay();
return rv;
}
#define SCC_ACCESS_INIT(port) \
unsigned char *_scc_shadow = &scc_shadow[port->channel][0]
#define SCCwrite(reg,val) _SCCwrite(port,_scc_shadow,scc_del,(reg),(val),1)
#define SCCwrite_NB(reg,val) _SCCwrite(port,_scc_shadow,scc_del,(reg),(val),0)
#define SCCread(reg) _SCCread(port,_scc_shadow,scc_del,(reg),1)
#define SCCread_NB(reg) _SCCread(port,_scc_shadow,scc_del,(reg),0)
#define SCCmod(reg,and,or) SCCwrite((reg),(SCCread(reg)&(and))|(or))
#endif /* _SCC_H */
drivers/staging/Kconfig
浏览文件 @ 6eafa460
......@@ -64,6 +64,8 @@ source "drivers/staging/rtl8712/Kconfig"
source "drivers/staging/rts_pstor/Kconfig"
source "drivers/staging/rts5139/Kconfig"
source "drivers/staging/frontier/Kconfig"
source "drivers/staging/pohmelfs/Kconfig"
......@@ -126,8 +128,6 @@ source "drivers/staging/quickstart/Kconfig"
source "drivers/staging/sbe-2t3e3/Kconfig"
source "drivers/staging/ath6kl/Kconfig"
source "drivers/staging/keucr/Kconfig"
source "drivers/staging/bcm/Kconfig"
......
drivers/staging/Makefile
浏览文件 @ 6eafa460
......@@ -25,6 +25,7 @@ obj-$(CONFIG_RTL8192U) += rtl8192u/
obj-$(CONFIG_RTL8192E) += rtl8192e/
obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_RTS_PSTOR) += rts_pstor/
obj-$(CONFIG_RTS5139) += rts5139/
obj-$(CONFIG_SPECTRA) += spectra/
obj-$(CONFIG_TRANZPORT) += frontier/
obj-$(CONFIG_POHMELFS) += pohmelfs/
......@@ -54,7 +55,6 @@ obj-$(CONFIG_SOLO6X10) += solo6x10/
obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/
obj-$(CONFIG_ACPI_QUICKSTART) += quickstart/
obj-$(CONFIG_SBE_2T3E3) += sbe-2t3e3/
obj-$(CONFIG_ATH6K_LEGACY) += ath6kl/
obj-$(CONFIG_USB_ENESTORAGE) += keucr/
obj-$(CONFIG_BCM_WIMAX) += bcm/
obj-$(CONFIG_FT1000) += ft1000/
......
drivers/staging/altera-stapl/altera.c
浏览文件 @ 6eafa460
......@@ -28,6 +28,7 @@
#include <linux/string.h>
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/module.h>
#include "altera.h"
#include "altera-exprt.h"
#include "altera-jtag.h"
......@@ -2384,7 +2385,7 @@ static int altera_get_act_info(u8 *p,
act_proc_attribute =
(p[proc_table + (13 * act_proc_id) + 8] & 0x03);
procptr = (struct altera_procinfo *)
procptr =
kzalloc(sizeof(struct altera_procinfo),
GFP_KERNEL);
......
drivers/staging/ath6kl/Kconfig 已删除 100644 → 0
浏览文件 @ c6a389f1
config ATH6K_LEGACY
tristate "Atheros AR6003 support (non mac80211)"
depends on MMC && WLAN
depends on CFG80211
select WIRELESS_EXT
select WEXT_PRIV
help
This module adds support for wireless adapters based on Atheros AR6003 chipset running over SDIO. If you choose to build it as a module, it will be called ath6kl. Pls note that AR6002 and AR6001 are not supported by this driver.
choice
prompt "AR6003 Board Data Configuration"
depends on ATH6K_LEGACY
default AR600x_SD31_XXX
help
Select the appropriate board data template from the list below that matches your AR6003 based reference design.
config AR600x_SD31_XXX
bool "SD31-xxx"
help
Board Data file for a standard SD31 reference design (File: bdata.SD31.bin)
config AR600x_WB31_XXX
bool "WB31-xxx"
help
Board Data file for a standard WB31 (BT/WiFi) reference design (File: bdata.WB31.bin)
config AR600x_SD32_XXX
bool "SD32-xxx"
help
Board Data file for a standard SD32 (5GHz) reference design (File: bdata.SD32.bin)
config AR600x_CUSTOM_XXX
bool "CUSTOM-xxx"
help
Board Data file for a custom reference design (File: should be named as bdata.CUSTOM.bin)
endchoice
config ATH6KL_ENABLE_COEXISTENCE
bool "BT Coexistence support"
depends on ATH6K_LEGACY
help
Enables WLAN/BT coexistence support. Select the apprpriate configuration from below.
choice
prompt "Front-End Antenna Configuration"
depends on ATH6KL_ENABLE_COEXISTENCE
default AR600x_DUAL_ANTENNA
help
Indicates the number of antennas being used by BT and WLAN. Select the appropriate configuration from the list below that matches your AR6003 based reference design.
config AR600x_DUAL_ANTENNA
bool "Dual Antenna"
help
Dual Antenna Design
config AR600x_SINGLE_ANTENNA
bool "Single Antenna"
help
Single Antenna Design
endchoice
choice
prompt "Collocated Bluetooth Type"
depends on ATH6KL_ENABLE_COEXISTENCE
default AR600x_BT_AR3001
help
Select the appropriate configuration from the list below that matches your AR6003 based reference design.
config AR600x_BT_QCOM
bool "Qualcomm BTS4020X"
help
Qualcomm BT (3 Wire PTA)
config AR600x_BT_CSR
bool "CSR BC06"
help
CSR BT (3 Wire PTA)
config AR600x_BT_AR3001
bool "Atheros AR3001"
help
Atheros BT (3 Wire PTA)
endchoice
config ATH6KL_HCI_BRIDGE
bool "HCI over SDIO support"
depends on ATH6K_LEGACY
help
Enables BT over SDIO. Applicable only for combo designs (eg: WB31)
config ATH6KL_CONFIG_GPIO_BT_RESET
bool "Configure BT Reset GPIO"
depends on ATH6KL_HCI_BRIDGE
help
Configure a WLAN GPIO for use with BT.
config AR600x_BT_RESET_PIN
int "GPIO"
depends on ATH6KL_CONFIG_GPIO_BT_RESET
default 22
help
WLAN GPIO to be used for resetting BT
config ATH6KL_HTC_RAW_INTERFACE
bool "RAW HTC support"
depends on ATH6K_LEGACY
help
Enables raw HTC interface. Allows application to directly talk to the HTC interface via the ioctl interface
config ATH6KL_VIRTUAL_SCATTER_GATHER
bool "Virtual Scatter-Gather support"
depends on ATH6K_LEGACY
help
Enables virtual scatter gather support for the hardware that does not support it natively.
config ATH6KL_SKIP_ABI_VERSION_CHECK
bool "Skip ABI version check support"
depends on ATH6K_LEGACY
help
Forces the driver to disable ABI version check. Caution: Incompatilbity between the host driver and target firmware may lead to unknown side effects.
config ATH6KL_BT_UART_FC_POLARITY
int "UART Flow Control Polarity"
depends on ATH6KL_LEGACY
default 0
help
Configures the polarity of UART Flow Control. A value of 0 implies active low and is the default setting. Set it to 1 for active high.
config ATH6KL_DEBUG
bool "Debug support"
depends on ATH6K_LEGACY
help
Enables debug support
config ATH6KL_ENABLE_HOST_DEBUG
bool "Host Debug support"
depends on ATH6KL_DEBUG
help
Enables debug support in the driver
config ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
bool "Target Debug support - Enable UART prints"
depends on ATH6KL_DEBUG
help
Enables uart prints
config AR600x_DEBUG_UART_TX_PIN
int "GPIO"
depends on ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
default 8
help
WLAN GPIO to be used for Debug UART (Tx)
config ATH6KL_DISABLE_TARGET_DBGLOGS
bool "Target Debug support - Disable Debug logs"
depends on ATH6KL_DEBUG
help
Enables debug logs
drivers/staging/ath6kl/Makefile 已删除 100644 → 0
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#------------------------------------------------------------------------------
# Copyright (c) 2004-2010 Atheros Communications Inc.
# All rights reserved.
#
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
#
#
#
# Author(s): ="Atheros"
#------------------------------------------------------------------------------
ccflags-y += -I$(obj)/include
ccflags-y += -I$(obj)/include/common
ccflags-y += -I$(obj)/wlan/include
ccflags-y += -I$(obj)/os/linux/include
ccflags-y += -I$(obj)/os
ccflags-y += -I$(obj)/bmi/include
ccflags-y += -I$(obj)/include/common/AR6002/hw4.0
ifeq ($(CONFIG_AR600x_DUAL_ANTENNA),y)
ccflags-y += -DAR600x_DUAL_ANTENNA
endif
ifeq ($(CONFIG_AR600x_SINGLE_ANTENNA),y)
ccflags-y += -DAR600x_SINGLE_ANTENNA
endif
ifeq ($(CONFIG_AR600x_BT_QCOM),y)
ccflags-y += -DAR600x_BT_QCOM
endif
ifeq ($(CONFIG_AR600x_BT_CSR),y)
ccflags-y += -DAR600x_BT_CSR
endif
ifeq ($(CONFIG_AR600x_BT_AR3001),y)
ccflags-y += -DAR600x_BT_AR3001
endif
ifeq ($(CONFIG_ATH6KL_HCI_BRIDGE),y)
ccflags-y += -DATH_AR6K_ENABLE_GMBOX
ccflags-y += -DHCI_TRANSPORT_SDIO
ccflags-y += -DSETUPHCI_ENABLED
ccflags-y += -DSETUPBTDEV_ENABLED
ath6kl-y += htc2/AR6000/ar6k_gmbox.o
ath6kl-y += htc2/AR6000/ar6k_gmbox_hciuart.o
ath6kl-y += miscdrv/ar3kconfig.o
ath6kl-y += miscdrv/ar3kps/ar3kpsconfig.o
ath6kl-y += miscdrv/ar3kps/ar3kpsparser.o
endif
ifeq ($(CONFIG_ATH6KL_CONFIG_GPIO_BT_RESET),y)
ccflags-y += -DATH6KL_CONFIG_GPIO_BT_RESET
endif
ifeq ($(CONFIG_ATH6KL_HTC_RAW_INTERFACE),y)
ccflags-y += -DHTC_RAW_INTERFACE
endif
ifeq ($(CONFIG_ATH6KL_ENABLE_HOST_DEBUG),y)
ccflags-y += -DDEBUG
ccflags-y += -DATH_DEBUG_MODULE
endif
ifeq ($(CONFIG_ATH6KL_ENABLE_TARGET_DEBUG_PRINTS),y)
ccflags-y += -DENABLEUARTPRINT_SET
endif
ifeq ($(CONFIG_ATH6KL_DISABLE_TARGET_DBGLOGS),y)
ccflags-y += -DATH6KL_DISABLE_TARGET_DBGLOGS
endif
ifeq ($(CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER),y)
ccflags-y += -DATH6KL_CONFIG_HIF_VIRTUAL_SCATTER
endif
ifeq ($(CONFIG_ATH6KL_SKIP_ABI_VERSION_CHECK),y)
ccflags-y += -DATH6KL_SKIP_ABI_VERSION_CHECK
endif
ccflags-y += -DWAPI_ENABLE
ccflags-y += -DCHECKSUM_OFFLOAD
obj-$(CONFIG_ATH6K_LEGACY) := ath6kl.o
ath6kl-y += htc2/AR6000/ar6k.o
ath6kl-y += htc2/AR6000/ar6k_events.o
ath6kl-y += htc2/htc_send.o
ath6kl-y += htc2/htc_recv.o
ath6kl-y += htc2/htc_services.o
ath6kl-y += htc2/htc.o
ath6kl-y += bmi/src/bmi.o
ath6kl-y += os/linux/cfg80211.o
ath6kl-y += os/linux/ar6000_drv.o
ath6kl-y += os/linux/ar6000_raw_if.o
ath6kl-y += os/linux/ar6000_pm.o
ath6kl-y += os/linux/netbuf.o
ath6kl-y += os/linux/hci_bridge.o
ath6kl-y += miscdrv/common_drv.o
ath6kl-y += miscdrv/credit_dist.o
ath6kl-y += wmi/wmi.o
ath6kl-y += reorder/rcv_aggr.o
ath6kl-y += wlan/src/wlan_node.o
ath6kl-y += wlan/src/wlan_recv_beacon.o
ath6kl-y += wlan/src/wlan_utils.o
# ATH_HIF_TYPE := sdio
ccflags-y += -I$(obj)/hif/sdio/linux_sdio/include
ccflags-y += -DSDIO
ath6kl-y += hif/sdio/linux_sdio/src/hif.o
ath6kl-y += hif/sdio/linux_sdio/src/hif_scatter.o
drivers/staging/ath6kl/TODO 已删除 100644 → 0
浏览文件 @ c6a389f1
TODO:
We are working hard on cleaning up the driver. There's sooooooooo much todo
so instead of editing this file please use the wiki:
http://wireless.kernel.org/en/users/Drivers/ath6kl
There's a respective TODO page there. Please also subscribe to the wiki page
to get e-mail updates on changes.
IRC:
We *really* need to coordinate development for ath6kl as the cleanup
patches will break pretty much any other patches. Please use IRC to
help coordinate better:
irc.freenode.net
#ath6kl
Send patches to:
- Greg Kroah-Hartman <greg@kroah.com>
- Luis R. Rodriguez <mcgrof@gmail.com>
- Joe Perches <joe@perches.com>
- Naveen Singh <nsingh@atheros.com>
drivers/staging/ath6kl/bmi/include/bmi_internal.h 已删除 100644 → 0
浏览文件 @ c6a389f1
//------------------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Communications Inc.
// All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef BMI_INTERNAL_H
#define BMI_INTERNAL_H
#include "a_config.h"
#include "athdefs.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME bmi
#include "a_debug.h"
#include "hw/mbox_host_reg.h"
#include "bmi_msg.h"
#define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)
#define BMI_COMMUNICATION_TIMEOUT 100000
/* ------ Global Variable Declarations ------- */
static bool bmiDone;
int
bmiBufferSend(struct hif_device *device,
u8 *buffer,
u32 length);
int
bmiBufferReceive(struct hif_device *device,
u8 *buffer,
u32 length,
bool want_timeout);
#endif
drivers/staging/ath6kl/bmi/src/bmi.c 已删除 100644 → 0
浏览文件 @ c6a389f1
此差异已折叠。
drivers/staging/ath6kl/hif/common/hif_sdio_common.h 已删除 100644 → 0
浏览文件 @ c6a389f1
//------------------------------------------------------------------------------
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// common header file for HIF modules designed for SDIO
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef HIF_SDIO_COMMON_H_
#define HIF_SDIO_COMMON_H_
/* SDIO manufacturer ID and Codes */
#define MANUFACTURER_ID_AR6002_BASE 0x200
#define MANUFACTURER_ID_AR6003_BASE 0x300
#define MANUFACTURER_ID_AR6K_BASE_MASK 0xFF00
#define FUNCTION_CLASS 0x0
#define MANUFACTURER_CODE 0x271 /* Atheros */
/* Mailbox address in SDIO address space */
#define HIF_MBOX_BASE_ADDR 0x800
#define HIF_MBOX_WIDTH 0x800
#define HIF_MBOX_START_ADDR(mbox) \
( HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH)
#define HIF_MBOX_END_ADDR(mbox) \
(HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1)
/* extended MBOX address for larger MBOX writes to MBOX 0*/
#define HIF_MBOX0_EXTENDED_BASE_ADDR 0x2800
#define HIF_MBOX0_EXTENDED_WIDTH_AR6002 (6*1024)
#define HIF_MBOX0_EXTENDED_WIDTH_AR6003 (18*1024)
/* version 1 of the chip has only a 12K extended mbox range */
#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1 0x4000
#define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1 (12*1024)
/* GMBOX addresses */
#define HIF_GMBOX_BASE_ADDR 0x7000
#define HIF_GMBOX_WIDTH 0x4000
/* for SDIO we recommend a 128-byte block size */
#define HIF_DEFAULT_IO_BLOCK_SIZE 128
/* set extended MBOX window information for SDIO interconnects */
static INLINE void SetExtendedMboxWindowInfo(u16 Manfid, struct hif_device_mbox_info *pInfo)
{
switch (Manfid & MANUFACTURER_ID_AR6K_BASE_MASK) {
case MANUFACTURER_ID_AR6002_BASE :
/* MBOX 0 has an extended range */
pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR;
pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6002;
break;
case MANUFACTURER_ID_AR6003_BASE :
/* MBOX 0 has an extended range */
pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1;
pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1;
pInfo->GMboxAddress = HIF_GMBOX_BASE_ADDR;
pInfo->GMboxSize = HIF_GMBOX_WIDTH;
break;
default:
A_ASSERT(false);
break;
}
}
/* special CCCR (func 0) registers */
#define CCCR_SDIO_IRQ_MODE_REG 0xF0 /* interrupt mode register */
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0) /* mode to enable special 4-bit interrupt assertion without clock*/
#endif /*HIF_SDIO_COMMON_H_*/
drivers/staging/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h 已删除 100644 → 0
浏览文件 @ c6a389f1
//------------------------------------------------------------------------------
// <copyright file="hif_internal.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// internal header file for hif layer
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _HIF_INTERNAL_H_
#define _HIF_INTERNAL_H_
#include "a_config.h"
#include "athdefs.h"
#include "a_osapi.h"
#include "hif.h"
#include "../../../common/hif_sdio_common.h"
#include <linux/scatterlist.h>
#define HIF_LINUX_MMC_SCATTER_SUPPORT
#define BUS_REQUEST_MAX_NUM 64
#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000
#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20
#define FLAGS_CARD_ENAB 0x02
#define FLAGS_CARD_IRQ_UNMSK 0x04
#define HIF_MBOX_BLOCK_SIZE HIF_DEFAULT_IO_BLOCK_SIZE
#define HIF_MBOX0_BLOCK_SIZE 1
#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
typedef struct bus_request {
struct bus_request *next; /* link list of available requests */
struct bus_request *inusenext; /* link list of in use requests */
struct semaphore sem_req;
u32 address; /* request data */
u8 *buffer;
u32 length;
u32 request;
void *context;
int status;
struct hif_scatter_req_priv *pScatterReq; /* this request is a scatter request */
} BUS_REQUEST;
struct hif_device {
struct sdio_func *func;
spinlock_t asynclock;
struct task_struct* async_task; /* task to handle async commands */
struct semaphore sem_async; /* wake up for async task */
int async_shutdown; /* stop the async task */
struct completion async_completion; /* thread completion */
BUS_REQUEST *asyncreq; /* request for async tasklet */
BUS_REQUEST *taskreq; /* async tasklet data */
spinlock_t lock;
BUS_REQUEST *s_busRequestFreeQueue; /* free list */
BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */
void *claimedContext;
HTC_CALLBACKS htcCallbacks;
u8 *dma_buffer;
struct dl_list ScatterReqHead; /* scatter request list head */
bool scatter_enabled; /* scatter enabled flag */
bool is_suspend;
bool is_disabled;
atomic_t irqHandling;
HIF_DEVICE_POWER_CHANGE_TYPE powerConfig;
const struct sdio_device_id *id;
};
#define HIF_DMA_BUFFER_SIZE (32 * 1024)
#define CMD53_FIXED_ADDRESS 1
#define CMD53_INCR_ADDRESS 2
BUS_REQUEST *hifAllocateBusRequest(struct hif_device *device);
void hifFreeBusRequest(struct hif_device *device, BUS_REQUEST *busrequest);
void AddToAsyncList(struct hif_device *device, BUS_REQUEST *busrequest);
#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
#define MAX_SCATTER_REQUESTS 4
#define MAX_SCATTER_ENTRIES_PER_REQ 16
#define MAX_SCATTER_REQ_TRANSFER_SIZE 32*1024
struct hif_scatter_req_priv {
struct hif_scatter_req *pHifScatterReq; /* HIF scatter request with allocated entries */
struct hif_device *device; /* this device */
BUS_REQUEST *busrequest; /* request associated with request */
/* scatter list for linux */
struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
};
#define ATH_DEBUG_SCATTER ATH_DEBUG_MAKE_MODULE_MASK(0)
int SetupHIFScatterSupport(struct hif_device *device, struct hif_device_scatter_support_info *pInfo);
void CleanupHIFScatterResources(struct hif_device *device);
int DoHifReadWriteScatter(struct hif_device *device, BUS_REQUEST *busrequest);
#else // HIF_LINUX_MMC_SCATTER_SUPPORT
static inline int SetupHIFScatterSupport(struct hif_device *device, struct hif_device_scatter_support_info *pInfo)
{
return A_ENOTSUP;
}
static inline int DoHifReadWriteScatter(struct hif_device *device, BUS_REQUEST *busrequest)
{
return A_ENOTSUP;
}
#define CleanupHIFScatterResources(d) { }
#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
#endif // _HIF_INTERNAL_H_
drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c 已删除 100644 → 0
浏览文件 @ c6a389f1
//------------------------------------------------------------------------------
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// HIF scatter implementation
//
// Author(s): ="Atheros"
//==============================================================================
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio.h>
#include <linux/kthread.h>
#include "hif_internal.h"
#define ATH_MODULE_NAME hif
#include "a_debug.h"
#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
#define _CMD53_ARG_READ 0
#define _CMD53_ARG_WRITE 1
#define _CMD53_ARG_BLOCK_BASIS 1
#define _CMD53_ARG_FIXED_ADDRESS 0
#define _CMD53_ARG_INCR_ADDRESS 1
#define SDIO_SET_CMD53_ARG(arg,rw,func,mode,opcode,address,bytes_blocks) \
(arg) = (((rw) & 1) << 31) | \
(((func) & 0x7) << 28) | \
(((mode) & 1) << 27) | \
(((opcode) & 1) << 26) | \
(((address) & 0x1FFFF) << 9) | \
((bytes_blocks) & 0x1FF)
static void FreeScatterReq(struct hif_device *device, struct hif_scatter_req *pReq)
{
unsigned long flag;
spin_lock_irqsave(&device->lock, flag);
DL_ListInsertTail(&device->ScatterReqHead, &pReq->ListLink);
spin_unlock_irqrestore(&device->lock, flag);
}
static struct hif_scatter_req *AllocScatterReq(struct hif_device *device)
{
struct dl_list *pItem;
unsigned long flag;
spin_lock_irqsave(&device->lock, flag);
pItem = DL_ListRemoveItemFromHead(&device->ScatterReqHead);
spin_unlock_irqrestore(&device->lock, flag);
if (pItem != NULL) {
return A_CONTAINING_STRUCT(pItem, struct hif_scatter_req, ListLink);
}
return NULL;
}
/* called by async task to perform the operation synchronously using direct MMC APIs */
int DoHifReadWriteScatter(struct hif_device *device, BUS_REQUEST *busrequest)
{
int i;
u8 rw;
u8 opcode;
struct mmc_request mmcreq;
struct mmc_command cmd;
struct mmc_data data;
struct hif_scatter_req_priv *pReqPriv;
struct hif_scatter_req *pReq;
int status = 0;
struct scatterlist *pSg;
pReqPriv = busrequest->pScatterReq;
A_ASSERT(pReqPriv != NULL);
pReq = pReqPriv->pHifScatterReq;
memset(&mmcreq, 0, sizeof(struct mmc_request));
memset(&cmd, 0, sizeof(struct mmc_command));
memset(&data, 0, sizeof(struct mmc_data));
data.blksz = HIF_MBOX_BLOCK_SIZE;
data.blocks = pReq->TotalLength / HIF_MBOX_BLOCK_SIZE;
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: (%s) Address: 0x%X, (BlockLen: %d, BlockCount: %d) , (tot:%d,sg:%d)\n",
(pReq->Request & HIF_WRITE) ? "WRITE":"READ", pReq->Address, data.blksz, data.blocks,
pReq->TotalLength,pReq->ValidScatterEntries));
if (pReq->Request & HIF_WRITE) {
rw = _CMD53_ARG_WRITE;
data.flags = MMC_DATA_WRITE;
} else {
rw = _CMD53_ARG_READ;
data.flags = MMC_DATA_READ;
}
if (pReq->Request & HIF_FIXED_ADDRESS) {
opcode = _CMD53_ARG_FIXED_ADDRESS;
} else {
opcode = _CMD53_ARG_INCR_ADDRESS;
}
/* fill SG entries */
pSg = pReqPriv->sgentries;
sg_init_table(pSg, pReq->ValidScatterEntries);
/* assemble SG list */
for (i = 0 ; i < pReq->ValidScatterEntries ; i++, pSg++) {
/* setup each sg entry */
if ((unsigned long)pReq->ScatterList[i].pBuffer & 0x3) {
/* note some scatter engines can handle unaligned buffers, print this
* as informational only */
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
("HIF: (%s) Scatter Buffer is unaligned 0x%lx\n",
pReq->Request & HIF_WRITE ? "WRITE":"READ",
(unsigned long)pReq->ScatterList[i].pBuffer));
}
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, (" %d: Addr:0x%lX, Len:%d \n",
i,(unsigned long)pReq->ScatterList[i].pBuffer,pReq->ScatterList[i].Length));
sg_set_buf(pSg, pReq->ScatterList[i].pBuffer, pReq->ScatterList[i].Length);
}
/* set scatter-gather table for request */
data.sg = pReqPriv->sgentries;
data.sg_len = pReq->ValidScatterEntries;
/* set command argument */
SDIO_SET_CMD53_ARG(cmd.arg,
rw,
device->func->num,
_CMD53_ARG_BLOCK_BASIS,
opcode,
pReq->Address,
data.blocks);
cmd.opcode = SD_IO_RW_EXTENDED;
cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
mmcreq.cmd = &cmd;
mmcreq.data = &data;
mmc_set_data_timeout(&data, device->func->card);
/* synchronous call to process request */
mmc_wait_for_req(device->func->card->host, &mmcreq);
if (cmd.error) {
status = A_ERROR;
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: cmd error: %d \n",cmd.error));
}
if (data.error) {
status = A_ERROR;
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: data error: %d \n",data.error));
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: FAILED!!! (%s) Address: 0x%X, Block mode (BlockLen: %d, BlockCount: %d)\n",
(pReq->Request & HIF_WRITE) ? "WRITE":"READ",pReq->Address, data.blksz, data.blocks));
}
/* set completion status, fail or success */
pReq->CompletionStatus = status;
if (pReq->Request & HIF_ASYNCHRONOUS) {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: async_task completion routine req: 0x%lX (%d)\n",(unsigned long)busrequest, status));
/* complete the request */
A_ASSERT(pReq->CompletionRoutine != NULL);
pReq->CompletionRoutine(pReq);
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER async_task upping busrequest : 0x%lX (%d)\n", (unsigned long)busrequest,status));
/* signal wait */
up(&busrequest->sem_req);
}
return status;
}
/* callback to issue a read-write scatter request */
static int HifReadWriteScatter(struct hif_device *device, struct hif_scatter_req *pReq)
{
int status = A_EINVAL;
u32 request = pReq->Request;
struct hif_scatter_req_priv *pReqPriv = (struct hif_scatter_req_priv *)pReq->HIFPrivate[0];
do {
A_ASSERT(pReqPriv != NULL);
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: total len: %d Scatter Entries: %d\n",
pReq->TotalLength, pReq->ValidScatterEntries));
if (!(request & HIF_EXTENDED_IO)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid command type: 0x%08x\n", request));
break;
}
if (!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS))) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid execution mode: 0x%08x\n", request));
break;
}
if (!(request & HIF_BLOCK_BASIS)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid data mode: 0x%08x\n", request));
break;
}
if (pReq->TotalLength > MAX_SCATTER_REQ_TRANSFER_SIZE) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid length: %d \n", pReq->TotalLength));
break;
}
if (pReq->TotalLength == 0) {
A_ASSERT(false);
break;
}
/* add bus request to the async list for the async I/O thread to process */
AddToAsyncList(device, pReqPriv->busrequest);
if (request & HIF_SYNCHRONOUS) {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued sync req: 0x%lX\n", (unsigned long)pReqPriv->busrequest));
/* signal thread and wait */
up(&device->sem_async);
if (down_interruptible(&pReqPriv->busrequest->sem_req) != 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,("HIF-SCATTER: interrupted! \n"));
/* interrupted, exit */
status = A_ERROR;
break;
} else {
status = pReq->CompletionStatus;
}
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued async req: 0x%lX\n", (unsigned long)pReqPriv->busrequest));
/* wake thread, it will process and then take care of the async callback */
up(&device->sem_async);
status = 0;
}
} while (false);
if (status && (request & HIF_ASYNCHRONOUS)) {
pReq->CompletionStatus = status;
pReq->CompletionRoutine(pReq);
status = 0;
}
return status;
}
/* setup of HIF scatter resources */
int SetupHIFScatterSupport(struct hif_device *device, struct hif_device_scatter_support_info *pInfo)
{
int status = A_ERROR;
int i;
struct hif_scatter_req_priv *pReqPriv;
BUS_REQUEST *busrequest;
do {
/* check if host supports scatter requests and it meets our requirements */
if (device->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : host only supports scatter of : %d entries, need: %d \n",
device->func->card->host->max_segs, MAX_SCATTER_ENTRIES_PER_REQ));
status = A_ENOTSUP;
break;
}
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HIF-SCATTER Enabled: max scatter req : %d entries: %d \n",
MAX_SCATTER_REQUESTS, MAX_SCATTER_ENTRIES_PER_REQ));
for (i = 0; i < MAX_SCATTER_REQUESTS; i++) {
/* allocate the private request blob */
pReqPriv = (struct hif_scatter_req_priv *)A_MALLOC(sizeof(struct hif_scatter_req_priv));
if (NULL == pReqPriv) {
break;
}
A_MEMZERO(pReqPriv, sizeof(struct hif_scatter_req_priv));
/* save the device instance*/
pReqPriv->device = device;
/* allocate the scatter request */
pReqPriv->pHifScatterReq = (struct hif_scatter_req *)A_MALLOC(sizeof(struct hif_scatter_req) +
(MAX_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(struct hif_scatter_item)));
if (NULL == pReqPriv->pHifScatterReq) {
kfree(pReqPriv);
break;
}
/* just zero the main part of the scatter request */
A_MEMZERO(pReqPriv->pHifScatterReq, sizeof(struct hif_scatter_req));
/* back pointer to the private struct */
pReqPriv->pHifScatterReq->HIFPrivate[0] = pReqPriv;
/* allocate a bus request for this scatter request */
busrequest = hifAllocateBusRequest(device);
if (NULL == busrequest) {
kfree(pReqPriv->pHifScatterReq);
kfree(pReqPriv);
break;
}
/* assign the scatter request to this bus request */
busrequest->pScatterReq = pReqPriv;
/* point back to the request */
pReqPriv->busrequest = busrequest;
/* add it to the scatter pool */
FreeScatterReq(device,pReqPriv->pHifScatterReq);
}
if (i != MAX_SCATTER_REQUESTS) {
status = A_NO_MEMORY;
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : failed to alloc scatter resources !\n"));
break;
}
/* set scatter function pointers */
pInfo->pAllocateReqFunc = AllocScatterReq;
pInfo->pFreeReqFunc = FreeScatterReq;
pInfo->pReadWriteScatterFunc = HifReadWriteScatter;
pInfo->MaxScatterEntries = MAX_SCATTER_ENTRIES_PER_REQ;
pInfo->MaxTransferSizePerScatterReq = MAX_SCATTER_REQ_TRANSFER_SIZE;
status = 0;
} while (false);
if (status) {
CleanupHIFScatterResources(device);
}
return status;
}
/* clean up scatter support */
void CleanupHIFScatterResources(struct hif_device *device)
{
struct hif_scatter_req_priv *pReqPriv;
struct hif_scatter_req *pReq;
/* empty the free list */
while (1) {
pReq = AllocScatterReq(device);
if (NULL == pReq) {
break;
}
pReqPriv = (struct hif_scatter_req_priv *)pReq->HIFPrivate[0];
A_ASSERT(pReqPriv != NULL);
if (pReqPriv->busrequest != NULL) {
pReqPriv->busrequest->pScatterReq = NULL;
/* free bus request */
hifFreeBusRequest(device, pReqPriv->busrequest);
pReqPriv->busrequest = NULL;
}
if (pReqPriv->pHifScatterReq != NULL) {
kfree(pReqPriv->pHifScatterReq);
pReqPriv->pHifScatterReq = NULL;
}
kfree(pReqPriv);
}
}
#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
drivers/staging/ath6kl/htc2/AR6000/ar6k.c 已删除 100644 → 0
浏览文件 @ c6a389f1
此差异已折叠。
drivers/staging/ath6kl/htc2/AR6000/ar6k.h 已删除 100644 → 0
浏览文件 @ c6a389f1
//------------------------------------------------------------------------------
// <copyright file="ar6k.h" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// AR6K device layer that handles register level I/O
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef AR6K_H_
#define AR6K_H_
#include "hci_transport_api.h"
#include "../htc_debug.h"
#define AR6K_MAILBOXES 4
/* HTC runs over mailbox 0 */
#define HTC_MAILBOX 0
#define AR6K_TARGET_DEBUG_INTR_MASK 0x01
#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \
INT_STATUS_ENABLE_CPU_MASK | \
INT_STATUS_ENABLE_COUNTER_MASK)
//#define MBOXHW_UNIT_TEST 1
PREPACK struct ar6k_irq_proc_registers {
u8 host_int_status;
u8 cpu_int_status;
u8 error_int_status;
u8 counter_int_status;
u8 mbox_frame;
u8 rx_lookahead_valid;
u8 host_int_status2;
u8 gmbox_rx_avail;
u32 rx_lookahead[2];
u32 rx_gmbox_lookahead_alias[2];
} POSTPACK;
#define AR6K_IRQ_PROC_REGS_SIZE sizeof(struct ar6k_irq_proc_registers)
PREPACK struct ar6k_irq_enable_registers {
u8 int_status_enable;
u8 cpu_int_status_enable;
u8 error_status_enable;
u8 counter_int_status_enable;
} POSTPACK;
PREPACK struct ar6k_gmbox_ctrl_registers {
u8 int_status_enable;
} POSTPACK;
#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(struct ar6k_irq_enable_registers)
#define AR6K_REG_IO_BUFFER_SIZE 32
#define AR6K_MAX_REG_IO_BUFFERS 8
#define FROM_DMA_BUFFER true
#define TO_DMA_BUFFER false
#define AR6K_SCATTER_ENTRIES_PER_REQ 16
#define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER 16*1024
#define AR6K_SCATTER_REQS 4
#define AR6K_LEGACY_MAX_WRITE_LENGTH 2048
#ifndef A_CACHE_LINE_PAD
#define A_CACHE_LINE_PAD 128
#endif
#define AR6K_MIN_SCATTER_ENTRIES_PER_REQ 2
#define AR6K_MIN_TRANSFER_SIZE_PER_SCATTER 4*1024
/* buffers for ASYNC I/O */
struct ar6k_async_reg_io_buffer {
struct htc_packet HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */
u8 _Pad1[A_CACHE_LINE_PAD];
u8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; /* cache-line safe with pads around */
u8 _Pad2[A_CACHE_LINE_PAD];
};
struct ar6k_gmbox_info {
void *pProtocolContext;
int (*pMessagePendingCallBack)(void *pContext, u8 LookAheadBytes[], int ValidBytes);
int (*pCreditsPendingCallback)(void *pContext, int NumCredits, bool CreditIRQEnabled);
void (*pTargetFailureCallback)(void *pContext, int Status);
void (*pStateDumpCallback)(void *pContext);
bool CreditCountIRQEnabled;
};
struct ar6k_device {
A_MUTEX_T Lock;
u8 _Pad1[A_CACHE_LINE_PAD];
struct ar6k_irq_proc_registers IrqProcRegisters; /* cache-line safe with pads around */
u8 _Pad2[A_CACHE_LINE_PAD];
struct ar6k_irq_enable_registers IrqEnableRegisters; /* cache-line safe with pads around */
u8 _Pad3[A_CACHE_LINE_PAD];
void *HIFDevice;
u32 BlockSize;
u32 BlockMask;
struct hif_device_mbox_info MailBoxInfo;
HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc;
void *HTCContext;
struct htc_packet_queue RegisterIOList;
struct ar6k_async_reg_io_buffer RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
void (*TargetFailureCallback)(void *Context);
int (*MessagePendingCallback)(void *Context,
u32 LookAheads[],
int NumLookAheads,
bool *pAsyncProc,
int *pNumPktsFetched);
HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode;
HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent;
bool HifAttached;
struct hif_device_irq_yield_params HifIRQYieldParams;
bool DSRCanYield;
int CurrentDSRRecvCount;
struct hif_device_scatter_support_info HifScatterInfo;
struct dl_list ScatterReqHead;
bool ScatterIsVirtual;
int MaxRecvBundleSize;
int MaxSendBundleSize;
struct ar6k_gmbox_info GMboxInfo;
bool GMboxEnabled;
struct ar6k_gmbox_ctrl_registers GMboxControlRegisters;
int RecheckIRQStatusCnt;
};
#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock);
#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock);
#define REF_IRQ_STATUS_RECHECK(p) (p)->RecheckIRQStatusCnt = 1 /* note: no need to lock this, it only gets set */
int DevSetup(struct ar6k_device *pDev);
void DevCleanup(struct ar6k_device *pDev);
int DevUnmaskInterrupts(struct ar6k_device *pDev);
int DevMaskInterrupts(struct ar6k_device *pDev);
int DevPollMboxMsgRecv(struct ar6k_device *pDev,
u32 *pLookAhead,
int TimeoutMS);
int DevRWCompletionHandler(void *context, int status);
int DevDsrHandler(void *context);
int DevCheckPendingRecvMsgsAsync(void *context);
void DevAsyncIrqProcessComplete(struct ar6k_device *pDev);
void DevDumpRegisters(struct ar6k_device *pDev,
struct ar6k_irq_proc_registers *pIrqProcRegs,
struct ar6k_irq_enable_registers *pIrqEnableRegs);
#define DEV_STOP_RECV_ASYNC true
#define DEV_STOP_RECV_SYNC false
#define DEV_ENABLE_RECV_ASYNC true
#define DEV_ENABLE_RECV_SYNC false
int DevStopRecv(struct ar6k_device *pDev, bool ASyncMode);
int DevEnableRecv(struct ar6k_device *pDev, bool ASyncMode);
int DevEnableInterrupts(struct ar6k_device *pDev);
int DevDisableInterrupts(struct ar6k_device *pDev);
int DevWaitForPendingRecv(struct ar6k_device *pDev,u32 TimeoutInMs,bool *pbIsRecvPending);
#define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
#define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length)
#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0)
static INLINE int DevSendPacket(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 SendLength) {
u32 paddedLength;
bool sync = (pPacket->Completion == NULL) ? true : false;
int status;
/* adjust the length to be a multiple of block size if appropriate */
paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, SendLength);
#if 0
if (paddedLength > pPacket->BufferLength) {
A_ASSERT(false);
if (pPacket->Completion != NULL) {
COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
return 0;
}
return A_EINVAL;
}
#endif
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
paddedLength,
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
sync ? "SYNC" : "ASYNC"));
status = HIFReadWrite(pDev->HIFDevice,
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
pPacket->pBuffer,
paddedLength, /* the padded length */
sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
if (sync) {
pPacket->Status = status;
} else {
if (status == A_PENDING) {
status = 0;
}
}
return status;
}
static INLINE int DevRecvPacket(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 RecvLength) {
u32 paddedLength;
int status;
bool sync = (pPacket->Completion == NULL) ? true : false;
/* adjust the length to be a multiple of block size if appropriate */
paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, RecvLength);
if (paddedLength > pPacket->BufferLength) {
A_ASSERT(false);
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
paddedLength,RecvLength,pPacket->BufferLength));
if (pPacket->Completion != NULL) {
COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
return 0;
}
return A_EINVAL;
}
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
("DevRecvPacket (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
(unsigned long)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
paddedLength,
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
sync ? "SYNC" : "ASYNC"));
status = HIFReadWrite(pDev->HIFDevice,
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
pPacket->pBuffer,
paddedLength,
sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
if (sync) {
pPacket->Status = status;
}
return status;
}
#define DEV_CHECK_RECV_YIELD(pDev) \
((pDev)->CurrentDSRRecvCount >= (pDev)->HifIRQYieldParams.RecvPacketYieldCount)
#define IS_DEV_IRQ_PROC_SYNC_MODE(pDev) (HIF_DEVICE_IRQ_SYNC_ONLY == (pDev)->HifIRQProcessingMode)
#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
/**************************************************/
/****** Scatter Function and Definitions
*
*
*/
int DevCopyScatterListToFromDMABuffer(struct hif_scatter_req *pReq, bool FromDMA);
/* copy any READ data back into scatter list */
#define DEV_FINISH_SCATTER_OPERATION(pR) \
do { \
if (!((pR)->CompletionStatus) && \
!((pR)->Request & HIF_WRITE) && \
((pR)->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) { \
(pR)->CompletionStatus = \
DevCopyScatterListToFromDMABuffer((pR), \
FROM_DMA_BUFFER); \
} \
} while (0)
/* copy any WRITE data to bounce buffer */
static INLINE int DEV_PREPARE_SCATTER_OPERATION(struct hif_scatter_req *pReq) {
if ((pReq->Request & HIF_WRITE) && (pReq->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) {
return DevCopyScatterListToFromDMABuffer(pReq,TO_DMA_BUFFER);
} else {
return 0;
}
}
int DevSetupMsgBundling(struct ar6k_device *pDev, int MaxMsgsPerTransfer);
int DevCleanupMsgBundling(struct ar6k_device *pDev);
#define DEV_GET_MAX_MSG_PER_BUNDLE(pDev) (pDev)->HifScatterInfo.MaxScatterEntries
#define DEV_GET_MAX_BUNDLE_LENGTH(pDev) (pDev)->HifScatterInfo.MaxTransferSizePerScatterReq
#define DEV_ALLOC_SCATTER_REQ(pDev) \
(pDev)->HifScatterInfo.pAllocateReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice)
#define DEV_FREE_SCATTER_REQ(pDev,pR) \
(pDev)->HifScatterInfo.pFreeReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice,(pR))
#define DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev) (pDev)->MaxRecvBundleSize
#define DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev) (pDev)->MaxSendBundleSize
#define DEV_SCATTER_READ true
#define DEV_SCATTER_WRITE false
#define DEV_SCATTER_ASYNC true
#define DEV_SCATTER_SYNC false
int DevSubmitScatterRequest(struct ar6k_device *pDev, struct hif_scatter_req *pScatterReq, bool Read, bool Async);
#ifdef MBOXHW_UNIT_TEST
int DoMboxHWTest(struct ar6k_device *pDev);
#endif
/* completely virtual */
struct dev_scatter_dma_virtual_info {
u8 *pVirtDmaBuffer; /* dma-able buffer - CPU accessible address */
u8 DataArea[1]; /* start of data area */
};
void DumpAR6KDevState(struct ar6k_device *pDev);
/**************************************************/
/****** GMBOX functions and definitions
*
*
*/
#ifdef ATH_AR6K_ENABLE_GMBOX
void DevCleanupGMbox(struct ar6k_device *pDev);
int DevSetupGMbox(struct ar6k_device *pDev);
int DevCheckGMboxInterrupts(struct ar6k_device *pDev);
void DevNotifyGMboxTargetFailure(struct ar6k_device *pDev);
#else
/* compiled out */
#define DevCleanupGMbox(p)
#define DevCheckGMboxInterrupts(p) 0
#define DevNotifyGMboxTargetFailure(p)
static INLINE int DevSetupGMbox(struct ar6k_device *pDev) {
pDev->GMboxEnabled = false;
return 0;
}
#endif
#ifdef ATH_AR6K_ENABLE_GMBOX
/* GMBOX protocol modules must expose each of these internal APIs */
HCI_TRANSPORT_HANDLE GMboxAttachProtocol(struct ar6k_device *pDev, struct hci_transport_config_info *pInfo);
int GMboxProtocolInstall(struct ar6k_device *pDev);
void GMboxProtocolUninstall(struct ar6k_device *pDev);
/* API used by GMBOX protocol modules */
struct ar6k_device *HTCGetAR6KDevice(void *HTCHandle);
#define DEV_GMBOX_SET_PROTOCOL(pDev,recv_callback,credits_pending,failure,statedump,context) \
{ \
(pDev)->GMboxInfo.pProtocolContext = (context); \
(pDev)->GMboxInfo.pMessagePendingCallBack = (recv_callback); \
(pDev)->GMboxInfo.pCreditsPendingCallback = (credits_pending); \
(pDev)->GMboxInfo.pTargetFailureCallback = (failure); \
(pDev)->GMboxInfo.pStateDumpCallback = (statedump); \
}
#define DEV_GMBOX_GET_PROTOCOL(pDev) (pDev)->GMboxInfo.pProtocolContext
int DevGMboxWrite(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 WriteLength);
int DevGMboxRead(struct ar6k_device *pDev, struct htc_packet *pPacket, u32 ReadLength);
#define PROC_IO_ASYNC true
#define PROC_IO_SYNC false
typedef enum GMBOX_IRQ_ACTION_TYPE {
GMBOX_ACTION_NONE = 0,
GMBOX_DISABLE_ALL,
GMBOX_ERRORS_IRQ_ENABLE,
GMBOX_RECV_IRQ_ENABLE,
GMBOX_RECV_IRQ_DISABLE,
GMBOX_CREDIT_IRQ_ENABLE,
GMBOX_CREDIT_IRQ_DISABLE,
} GMBOX_IRQ_ACTION_TYPE;
int DevGMboxIRQAction(struct ar6k_device *pDev, GMBOX_IRQ_ACTION_TYPE, bool AsyncMode);
int DevGMboxReadCreditCounter(struct ar6k_device *pDev, bool AsyncMode, int *pCredits);
int DevGMboxReadCreditSize(struct ar6k_device *pDev, int *pCreditSize);
int DevGMboxRecvLookAheadPeek(struct ar6k_device *pDev, u8 *pLookAheadBuffer, int *pLookAheadBytes);
int DevGMboxSetTargetInterrupt(struct ar6k_device *pDev, int SignalNumber, int AckTimeoutMS);
#endif
#endif /*AR6K_H_*/
drivers/staging/ath6kl/htc2/htc.c 已删除 100644 → 0
浏览文件 @ c6a389f1
此差异已折叠。
drivers/staging/ath6kl/htc2/htc_debug.h 已删除 100644 → 0
浏览文件 @ c6a389f1
//------------------------------------------------------------------------------
// <copyright file="htc_debug.h" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef HTC_DEBUG_H_
#define HTC_DEBUG_H_
#define ATH_MODULE_NAME htc
#include "a_debug.h"
/* ------- Debug related stuff ------- */
#define ATH_DEBUG_SEND ATH_DEBUG_MAKE_MODULE_MASK(0)
#define ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(1)
#define ATH_DEBUG_SYNC ATH_DEBUG_MAKE_MODULE_MASK(2)
#define ATH_DEBUG_DUMP ATH_DEBUG_MAKE_MODULE_MASK(3)
#define ATH_DEBUG_IRQ ATH_DEBUG_MAKE_MODULE_MASK(4)
#endif /*HTC_DEBUG_H_*/
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//------------------------------------------------------------------------------
// <copyright file="a_config.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// This file contains software configuration options that enables
// specific software "features"
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _A_CONFIG_H_
#define _A_CONFIG_H_
#include "../os/linux/include/config_linux.h"
#endif
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//------------------------------------------------------------------------------
// <copyright file="a_drv.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// This file contains the definitions of the basic atheros data types.
// It is used to map the data types in atheros files to a platform specific
// type.
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _A_DRV_H_
#define _A_DRV_H_
#include "../os/linux/include/athdrv_linux.h"
#endif /* _ADRV_H_ */
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drivers/staging/rtl8192e/dot11d.c 0 → 100644
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drivers/staging/rtl8192e/dot11d.h
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drivers/staging/rtl8192e/ieee80211/dot11d.c 已删除 100644 → 0
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drivers/staging/rtl8192e/ieee80211/dot11d.h 已删除 100644 → 0
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drivers/staging/rtl8192e/license 0 → 100644
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drivers/staging/rtl8192e/r8180_93cx6.c 已删除 100644 → 0
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drivers/staging/rtl8192e/r8180_93cx6.h 已删除 100644 → 0
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drivers/staging/rtl8192e/r8190P_def.h 0 → 100644
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drivers/staging/rtl8192e/r8190P_rtl8256.c 0 → 100644
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drivers/staging/rtl8192e/r8190P_rtl8256.h 0 → 100644
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drivers/staging/rtl8192e/r8190_rtl8256.c 已删除 100644 → 0
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drivers/staging/rtl8192e/r8190_rtl8256.h 已删除 100644 → 0
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drivers/staging/rtl8192e/r8192E.h 已删除 100644 → 0
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drivers/staging/rtl8192e/r8192E_cmdpkt.c 0 → 100644
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drivers/staging/rtl8192e/r8192E_cmdpkt.h 0 → 100644
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drivers/staging/rtl8192e/r8192E_core.c 已删除 100644 → 0
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drivers/staging/rtl8192e/r8192E_dev.c 0 → 100644
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drivers/staging/rtl8192e/r8192E_dev.h 0 → 100644
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drivers/staging/rtl8192e/r8192E_dm.c 已删除 100644 → 0
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drivers/staging/rtl8192e/r8192E_dm.h 已删除 100644 → 0
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drivers/staging/rtl8192e/r8192E_firmware.c 0 → 100644
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drivers/staging/rtl8192e/r8192E_firmware.h 0 → 100644
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drivers/staging/rtl8192e/r8192E_hwimg.c 0 → 100644
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drivers/staging/rtl8192e/r8192E_hwimg.h 0 → 100644
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drivers/staging/rtl8192e/r8192E_phy.c 0 → 100644
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drivers/staging/rtl8192e/r8192E_phy.h 0 → 100644
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drivers/staging/rtl8192e/r8192E_phyreg.h 0 → 100644
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drivers/staging/rtl8192e/r8192E_wx.h 已删除 100644 → 0
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drivers/staging/rtl8192e/r8192_pm.c 已删除 100644 → 0
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drivers/staging/rtl8192e/r8192_pm.h 已删除 100644 → 0
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drivers/staging/rtl8192e/r819xE_cmdpkt.c 已删除 100644 → 0
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drivers/staging/rtl8192e/r819xE_cmdpkt.h 已删除 100644 → 0
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drivers/staging/rtl8192e/r819xE_firmware.c 已删除 100644 → 0
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drivers/staging/rtl8192e/r819xE_phy.c 已删除 100644 → 0
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drivers/staging/rtl8192e/r819xE_phy.h 已删除 100644 → 0
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drivers/staging/rtl8192e/rtl819x_BAProc.c 0 → 100644
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drivers/staging/rtl8192e/rtl819x_HTProc.c 0 → 100644
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drivers/staging/rtl8192e/rtl819x_Qos.h 0 → 100644
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drivers/staging/rtl8192e/rtl819x_TSProc.c 0 → 100644
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drivers/staging/rtl8192e/rtl_cam.c 0 → 100644
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drivers/staging/rtl8192e/rtl_cam.h 0 → 100644
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drivers/staging/rtl8192e/rtl_core.c 0 → 100644
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drivers/staging/rtl8192e/rtl_core.h 0 → 100644
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drivers/staging/rtl8192e/rtl_debug.c 0 → 100644
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drivers/staging/rtl8192e/rtl_debug.h 0 → 100644
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drivers/staging/rtl8192e/rtl_dm.c 0 → 100644
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drivers/staging/rtl8192e/rtl_dm.h 0 → 100644
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drivers/staging/rtl8192e/rtl_eeprom.c 0 → 100644
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drivers/staging/rtl8192e/rtl_eeprom.h 0 → 100644
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drivers/staging/rtl8192e/rtl_ethtool.c 0 → 100644
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drivers/staging/rtl8192e/rtl_pci.c 0 → 100644
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drivers/staging/rtl8192e/rtl_pci.h 0 → 100644
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drivers/staging/rtl8192e/rtl_pm.c 0 → 100644
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drivers/staging/rtl8192e/rtl_pm.h 0 → 100644
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drivers/staging/rtl8192e/rtl_ps.c 0 → 100644
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drivers/staging/rtl8192e/rtl_ps.h 0 → 100644
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drivers/staging/rtl8192e/rtl_wx.h 0 → 100644
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drivers/staging/rtl8192e/rtllib_endianfree.h 0 → 100644
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drivers/staging/rtl8712/drv_types.h
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drivers/staging/rtl8712/ethernet.h
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drivers/staging/rtl8712/generic.h
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drivers/staging/rtl8712/if_ether.h
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drivers/staging/rtl8712/os_intfs.c
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drivers/staging/rtl8712/swab.h
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drivers/staging/rtl8712/usb_ops.h
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drivers/staging/rts5139/Kconfig 0 → 100644
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drivers/staging/rts5139/Makefile 0 → 100644
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drivers/staging/rts5139/TODO 0 → 100644
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drivers/staging/rts5139/debug.h 0 → 100644
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drivers/staging/rts5139/ms.c 0 → 100644
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drivers/staging/rts5139/ms.h 0 → 100644
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drivers/staging/rts5139/ms_mg.c 0 → 100644
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drivers/staging/rts5139/ms_mg.h 0 → 100644
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drivers/staging/rts5139/rts51x.c 0 → 100644
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drivers/staging/rts5139/rts51x.h 0 → 100644
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drivers/staging/rts5139/rts51x_card.c 0 → 100644
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drivers/staging/rts5139/rts51x_card.h 0 → 100644
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drivers/staging/rts5139/rts51x_chip.c 0 → 100644
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drivers/staging/rts5139/rts51x_chip.h 0 → 100644
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drivers/staging/rts5139/rts51x_fop.c 0 → 100644
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drivers/staging/rts5139/rts51x_fop.h 0 → 100644
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drivers/staging/rts5139/rts51x_scsi.c 0 → 100644
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drivers/staging/rts5139/rts51x_scsi.h 0 → 100644
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drivers/staging/rts5139/rts51x_sys.h 0 → 100644
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drivers/staging/rts5139/rts51x_transport.c 0 → 100644
浏览文件 @ 6eafa460
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drivers/staging/rts5139/rts51x_transport.h 0 → 100644
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drivers/staging/rts5139/sd.c 0 → 100644
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drivers/staging/rts5139/sd.h 0 → 100644
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drivers/staging/rts5139/sd_cprm.c 0 → 100644
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drivers/staging/rts5139/sd_cprm.h 0 → 100644
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drivers/staging/rts5139/trace.h 0 → 100644
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drivers/staging/rts5139/xd.c 0 → 100644
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drivers/staging/rts5139/xd.h 0 → 100644
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drivers/staging/rts_pstor/Makefile
浏览文件 @ 6eafa460
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drivers/staging/rts_pstor/sd.c
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drivers/staging/rts_pstor/spi.c
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drivers/staging/sm7xx/smtcfb.c
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drivers/staging/spectra/ffsport.c
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drivers/staging/usbip/stub.h
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drivers/staging/usbip/stub_dev.c
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drivers/staging/usbip/stub_main.c
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drivers/staging/usbip/stub_rx.c
浏览文件 @ 6eafa460
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drivers/staging/usbip/usbip_protocol.txt 0 → 100644
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drivers/staging/usbip/vhci.h
浏览文件 @ 6eafa460
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drivers/staging/vme/vme.c
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drivers/staging/vme/vme_bridge.h
浏览文件 @ 6eafa460
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drivers/staging/vt6655/IEEE11h.c
浏览文件 @ 6eafa460
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drivers/staging/vt6655/dpc.c
浏览文件 @ 6eafa460
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drivers/staging/vt6655/wmgr.c
浏览文件 @ 6eafa460
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drivers/staging/vt6656/dpc.c
浏览文件 @ 6eafa460
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drivers/staging/vt6656/main_usb.c
浏览文件 @ 6eafa460
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drivers/staging/vt6656/wmgr.c
浏览文件 @ 6eafa460
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drivers/staging/xgifb/XGI_main.h
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drivers/staging/xgifb/XGI_main_26.c
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drivers/staging/xgifb/XGIfb.h
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drivers/staging/xgifb/vb_def.h
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drivers/staging/xgifb/vb_ext.h
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drivers/staging/xgifb/vb_setmode.c
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drivers/staging/xgifb/vb_struct.h
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drivers/staging/xgifb/vb_table.h
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drivers/staging/xgifb/vgatypes.h
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drivers/staging/zram/zram_drv.c
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drivers/staging/zram/zram_drv.h
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drivers/staging/zram/zram_sysfs.c
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include/linux/mod_devicetable.h
浏览文件 @ 6eafa460
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scripts/mod/file2alias.c
浏览文件 @ 6eafa460
此差异已折叠。
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