提交 68556dd7 编写于 作者: X Xing Zheng 提交者: Heiko Stuebner

ARM: dts: rockchip: fix the pinctrl bias settings for rk3036

The pinctrl gpio pull up/down is incorrect since the rk3036 SoCs
can't set the status in the internal.

We should keep the default status for enable the gpio status,
In fact, the pull_none is the disable the gpio pull up/down.
Signed-off-by: NXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Reviewed-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
上级 4b0d98ae
...@@ -427,12 +427,8 @@ ...@@ -427,12 +427,8 @@
#interrupt-cells = <2>; #interrupt-cells = <2>;
}; };
pcfg_pull_up: pcfg-pull-up { pcfg_pull_default: pcfg_pull_default {
bias-pull-up; bias-pull-pin-default;
};
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
}; };
pcfg_pull_none: pcfg-pull-none { pcfg_pull_none: pcfg-pull-none {
...@@ -473,18 +469,18 @@ ...@@ -473,18 +469,18 @@
}; };
emmc_cmd: emmc-cmd { emmc_cmd: emmc-cmd {
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
}; };
emmc_bus8: emmc-bus8 { emmc_bus8: emmc-bus8 {
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
<1 25 RK_FUNC_2 &pcfg_pull_none>, <1 25 RK_FUNC_2 &pcfg_pull_default>,
<1 26 RK_FUNC_2 &pcfg_pull_none>, <1 26 RK_FUNC_2 &pcfg_pull_default>,
<1 27 RK_FUNC_2 &pcfg_pull_none>, <1 27 RK_FUNC_2 &pcfg_pull_default>,
<1 28 RK_FUNC_2 &pcfg_pull_none>, <1 28 RK_FUNC_2 &pcfg_pull_default>,
<1 29 RK_FUNC_2 &pcfg_pull_none>, <1 29 RK_FUNC_2 &pcfg_pull_default>,
<1 30 RK_FUNC_2 &pcfg_pull_none>, <1 30 RK_FUNC_2 &pcfg_pull_default>,
<1 31 RK_FUNC_2 &pcfg_pull_none>; <1 31 RK_FUNC_2 &pcfg_pull_default>;
}; };
}; };
...@@ -522,12 +518,12 @@ ...@@ -522,12 +518,12 @@
uart0 { uart0 {
uart0_xfer: uart0-xfer { uart0_xfer: uart0-xfer {
rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_up>, rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
<0 17 RK_FUNC_1 &pcfg_pull_none>; <0 17 RK_FUNC_1 &pcfg_pull_none>;
}; };
uart0_cts: uart0-cts { uart0_cts: uart0-cts {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_up>; rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
}; };
uart0_rts: uart0-rts { uart0_rts: uart0-rts {
...@@ -537,7 +533,7 @@ ...@@ -537,7 +533,7 @@
uart1 { uart1 {
uart1_xfer: uart1-xfer { uart1_xfer: uart1-xfer {
rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
<2 23 RK_FUNC_1 &pcfg_pull_none>; <2 23 RK_FUNC_1 &pcfg_pull_none>;
}; };
/* no rts / cts for uart1 */ /* no rts / cts for uart1 */
...@@ -545,7 +541,7 @@ ...@@ -545,7 +541,7 @@
uart2 { uart2 {
uart2_xfer: uart2-xfer { uart2_xfer: uart2-xfer {
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
<1 19 RK_FUNC_2 &pcfg_pull_none>; <1 19 RK_FUNC_2 &pcfg_pull_none>;
}; };
/* no rts / cts for uart2 */ /* no rts / cts for uart2 */
......
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