MIPS: introduce CPU_R4K_CACHE_TLB
R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to remove some lines in arch/mips/mm/Makefile. Signed-off-by: NFlorian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/3328/Signed-off-by: NJohn Crispin <blogic@openwrt.org>
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