提交 5a7a1eeb 编写于 作者: H Hersen Wu 提交者: Alex Deucher

drm/amd/display: set HBR3 and TPS4 capable flags

Signed-off-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NZeyu Fan <Zeyu.Fan@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 aff20230
...@@ -1068,9 +1068,19 @@ bool dce110_link_encoder_construct( ...@@ -1068,9 +1068,19 @@ bool dce110_link_encoder_construct(
&bp_cap_info)) &bp_cap_info))
enc110->base.features.flags.bits.IS_HBR2_CAPABLE = enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
bp_cap_info.DP_HBR2_CAP; bp_cap_info.DP_HBR2_CAP;
enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
bp_cap_info.DP_HBR3_EN;
} }
/* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes,
* IS_HBR3_CAPABLE = 0.
*/
/* test pattern 3 support */ /* test pattern 3 support */
enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true; enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
/* test pattern 4 support */
enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false; enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false;
/* /*
......
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