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提交 54ef0ec2 编写于 作者: B Becky Bruce 提交者： Kumar Gala
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[POWERPC] Delete unused fec_8xx net driver 

This driver has been superseded by fs_enet and is no longer in use.
Signed-off-by: NBecky Bruce <becky.bruce@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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drivers/net/Kconfig
浏览文件 @ 54ef0ec2
......@@ -1884,7 +1884,6 @@ config NE_H8300
Say Y here if you want to use the NE2000 compatible
controller on the Renesas H8/300 processor.
source "drivers/net/fec_8xx/Kconfig"
source "drivers/net/fs_enet/Kconfig"
endif # NET_ETHERNET
......
drivers/net/Makefile
浏览文件 @ 54ef0ec2
......@@ -217,7 +217,6 @@ obj-$(CONFIG_SMC91X) += smc91x.o
obj-$(CONFIG_SMC911X) += smc911x.o
obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
obj-$(CONFIG_DM9000) += dm9000.o
obj-$(CONFIG_FEC_8XX) += fec_8xx/
obj-$(CONFIG_PASEMI_MAC) += pasemi_mac_driver.o
pasemi_mac_driver-objs := pasemi_mac.o pasemi_mac_ethtool.o
obj-$(CONFIG_MLX4_CORE) += mlx4/
......
drivers/net/fec_8xx/Kconfig 已删除 100644 → 0
浏览文件 @ bfd123bf
config FEC_8XX
tristate "Motorola 8xx FEC driver"
depends on 8XX
select MII
config FEC_8XX_GENERIC_PHY
bool "Support any generic PHY"
depends on FEC_8XX
default y
config FEC_8XX_DM9161_PHY
bool "Support DM9161 PHY"
depends on FEC_8XX
default n
config FEC_8XX_LXT971_PHY
bool "Support LXT971/LXT972 PHY"
depends on FEC_8XX
default n
drivers/net/fec_8xx/Makefile 已删除 100644 → 0
浏览文件 @ bfd123bf
#
# Makefile for the Motorola 8xx FEC ethernet controller
#
obj-$(CONFIG_FEC_8XX) += fec_8xx.o
fec_8xx-objs := fec_main.o fec_mii.o
# the platform instantatiation objects
ifeq ($(CONFIG_NETTA),y)
fec_8xx-objs += fec_8xx-netta.o
endif
drivers/net/fec_8xx/fec_8xx-netta.c 已删除 100644 → 0
浏览文件 @ bfd123bf
/*
* FEC instantatiation file for NETTA
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/bitops.h>
#include <asm/8xx_immap.h>
#include <asm/pgtable.h>
#include <asm/mpc8xx.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/cpm1.h>
#include "fec_8xx.h"
/*************************************************/
static struct fec_platform_info fec1_info = {
.fec_no = 0,
.use_mdio = 1,
.phy_addr = 8,
.fec_irq = SIU_LEVEL1,
.phy_irq = CPM_IRQ_OFFSET + CPMVEC_PIO_PC6,
.rx_ring = 128,
.tx_ring = 16,
.rx_copybreak = 240,
.use_napi = 1,
.napi_weight = 17,
};
static struct fec_platform_info fec2_info = {
.fec_no = 1,
.use_mdio = 1,
.phy_addr = 2,
.fec_irq = SIU_LEVEL3,
.phy_irq = CPM_IRQ_OFFSET + CPMVEC_PIO_PC7,
.rx_ring = 128,
.tx_ring = 16,
.rx_copybreak = 240,
.use_napi = 1,
.napi_weight = 17,
};
static struct net_device *fec1_dev;
static struct net_device *fec2_dev;
/* XXX custom u-boot & Linux startup needed */
extern const char *__fw_getenv(const char *var);
/* access ports */
#define setbits32(_addr, _v) __fec_out32(&(_addr), __fec_in32(&(_addr)) | (_v))
#define clrbits32(_addr, _v) __fec_out32(&(_addr), __fec_in32(&(_addr)) & ~(_v))
#define setbits16(_addr, _v) __fec_out16(&(_addr), __fec_in16(&(_addr)) | (_v))
#define clrbits16(_addr, _v) __fec_out16(&(_addr), __fec_in16(&(_addr)) & ~(_v))
int fec_8xx_platform_init(void)
{
immap_t *immap = (immap_t *)IMAP_ADDR;
bd_t *bd = (bd_t *) __res;
const char *s;
char *e;
int i;
/* use MDC for MII */
setbits16(immap->im_ioport.iop_pdpar, 0x0080);
clrbits16(immap->im_ioport.iop_pddir, 0x0080);
/* configure FEC1 pins */
setbits16(immap->im_ioport.iop_papar, 0xe810);
setbits16(immap->im_ioport.iop_padir, 0x0810);
clrbits16(immap->im_ioport.iop_padir, 0xe000);
setbits32(immap->im_cpm.cp_pbpar, 0x00000001);
clrbits32(immap->im_cpm.cp_pbdir, 0x00000001);
setbits32(immap->im_cpm.cp_cptr, 0x00000100);
clrbits32(immap->im_cpm.cp_cptr, 0x00000050);
clrbits16(immap->im_ioport.iop_pcpar, 0x0200);
clrbits16(immap->im_ioport.iop_pcdir, 0x0200);
clrbits16(immap->im_ioport.iop_pcso, 0x0200);
setbits16(immap->im_ioport.iop_pcint, 0x0200);
/* configure FEC2 pins */
setbits32(immap->im_cpm.cp_pepar, 0x00039620);
setbits32(immap->im_cpm.cp_pedir, 0x00039620);
setbits32(immap->im_cpm.cp_peso, 0x00031000);
clrbits32(immap->im_cpm.cp_peso, 0x00008620);
setbits32(immap->im_cpm.cp_cptr, 0x00000080);
clrbits32(immap->im_cpm.cp_cptr, 0x00000028);
clrbits16(immap->im_ioport.iop_pcpar, 0x0200);
clrbits16(immap->im_ioport.iop_pcdir, 0x0200);
clrbits16(immap->im_ioport.iop_pcso, 0x0200);
setbits16(immap->im_ioport.iop_pcint, 0x0200);
/* fill up */
fec1_info.sys_clk = bd->bi_intfreq;
fec2_info.sys_clk = bd->bi_intfreq;
s = __fw_getenv("ethaddr");
if (s != NULL) {
for (i = 0; i < 6; i++) {
fec1_info.macaddr[i] = simple_strtoul(s, &e, 16);
if (*e)
s = e + 1;
}
}
s = __fw_getenv("eth1addr");
if (s != NULL) {
for (i = 0; i < 6; i++) {
fec2_info.macaddr[i] = simple_strtoul(s, &e, 16);
if (*e)
s = e + 1;
}
}
fec_8xx_init_one(&fec1_info, &fec1_dev);
fec_8xx_init_one(&fec2_info, &fec2_dev);
return fec1_dev != NULL && fec2_dev != NULL ? 0 : -1;
}
void fec_8xx_platform_cleanup(void)
{
if (fec2_dev != NULL)
fec_8xx_cleanup_one(fec2_dev);
if (fec1_dev != NULL)
fec_8xx_cleanup_one(fec1_dev);
}
drivers/net/fec_8xx/fec_8xx.h 已删除 100644 → 0
浏览文件 @ bfd123bf
#ifndef FEC_8XX_H
#define FEC_8XX_H
#include <linux/mii.h>
#include <linux/netdevice.h>
#include <linux/types.h>
/* HW info */
/* CRC polynomium used by the FEC for the multicast group filtering */
#define FEC_CRC_POLY 0x04C11DB7
#define MII_ADVERTISE_HALF (ADVERTISE_100HALF | \
ADVERTISE_10HALF | ADVERTISE_CSMA)
#define MII_ADVERTISE_ALL (ADVERTISE_100FULL | \
ADVERTISE_10FULL | MII_ADVERTISE_HALF)
/* Interrupt events/masks.
*/
#define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */
#define FEC_ENET_BABR 0x40000000U /* Babbling receiver */
#define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */
#define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */
#define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
#define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */
#define FEC_ENET_RXF 0x02000000U /* Full frame received */
#define FEC_ENET_RXB 0x01000000U /* A buffer was received */
#define FEC_ENET_MII 0x00800000U /* MII interrupt */
#define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */
#define FEC_ECNTRL_PINMUX 0x00000004
#define FEC_ECNTRL_ETHER_EN 0x00000002
#define FEC_ECNTRL_RESET 0x00000001
#define FEC_RCNTRL_BC_REJ 0x00000010
#define FEC_RCNTRL_PROM 0x00000008
#define FEC_RCNTRL_MII_MODE 0x00000004
#define FEC_RCNTRL_DRT 0x00000002
#define FEC_RCNTRL_LOOP 0x00000001
#define FEC_TCNTRL_FDEN 0x00000004
#define FEC_TCNTRL_HBC 0x00000002
#define FEC_TCNTRL_GTS 0x00000001
/* values for MII phy_status */
#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
#define PHY_STAT_SPMASK 0xf000 /* mask for speed */
#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
typedef struct phy_info {
unsigned int id;
const char *name;
void (*startup) (struct net_device * dev);
void (*shutdown) (struct net_device * dev);
void (*ack_int) (struct net_device * dev);
} phy_info_t;
/* The FEC stores dest/src/type, data, and checksum for receive packets.
*/
#define MAX_MTU 1508 /* Allow fullsized pppoe packets over VLAN */
#define MIN_MTU 46 /* this is data size */
#define CRC_LEN 4
#define PKT_MAXBUF_SIZE (MAX_MTU+ETH_HLEN+CRC_LEN)
#define PKT_MINBUF_SIZE (MIN_MTU+ETH_HLEN+CRC_LEN)
/* Must be a multiple of 4 */
#define PKT_MAXBLR_SIZE ((PKT_MAXBUF_SIZE+3) & ~3)
/* This is needed so that invalidate_xxx wont invalidate too much */
#define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE)
/* platform interface */
struct fec_platform_info {
int fec_no; /* FEC index */
int use_mdio; /* use external MII */
int phy_addr; /* the phy address */
int fec_irq, phy_irq; /* the irq for the controller */
int rx_ring, tx_ring; /* number of buffers on rx */
int sys_clk; /* system clock */
__u8 macaddr[6]; /* mac address */
int rx_copybreak; /* limit we copy small frames */
int use_napi; /* use NAPI */
int napi_weight; /* NAPI weight */
};
/* forward declaration */
struct fec;
struct fec_enet_private {
spinlock_t lock; /* during all ops except TX pckt processing */
spinlock_t tx_lock; /* during fec_start_xmit and fec_tx */
struct net_device *dev;
struct napi_struct napi;
int fecno;
struct fec *fecp;
const struct fec_platform_info *fpi;
int rx_ring, tx_ring;
dma_addr_t ring_mem_addr;
void *ring_base;
struct sk_buff **rx_skbuff;
struct sk_buff **tx_skbuff;
cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
cbd_t *tx_bd_base;
cbd_t *dirty_tx; /* ring entries to be free()ed. */
cbd_t *cur_rx;
cbd_t *cur_tx;
int tx_free;
struct net_device_stats stats;
struct timer_list phy_timer_list;
const struct phy_info *phy;
unsigned int fec_phy_speed;
__u32 msg_enable;
struct mii_if_info mii_if;
};
/***************************************************************************/
void fec_restart(struct net_device *dev, int duplex, int speed);
void fec_stop(struct net_device *dev);
/***************************************************************************/
int fec_mii_read(struct net_device *dev, int phy_id, int location);
void fec_mii_write(struct net_device *dev, int phy_id, int location, int value);
int fec_mii_phy_id_detect(struct net_device *dev);
void fec_mii_startup(struct net_device *dev);
void fec_mii_shutdown(struct net_device *dev);
void fec_mii_ack_int(struct net_device *dev);
void fec_mii_link_status_change_check(struct net_device *dev, int init_media);
/***************************************************************************/
#define FEC1_NO 0x00
#define FEC2_NO 0x01
#define FEC3_NO 0x02
int fec_8xx_init_one(const struct fec_platform_info *fpi,
struct net_device **devp);
int fec_8xx_cleanup_one(struct net_device *dev);
/***************************************************************************/
#define DRV_MODULE_NAME "fec_8xx"
#define PFX DRV_MODULE_NAME ": "
#define DRV_MODULE_VERSION "0.1"
#define DRV_MODULE_RELDATE "May 6, 2004"
/***************************************************************************/
int fec_8xx_platform_init(void);
void fec_8xx_platform_cleanup(void);
/***************************************************************************/
/* FEC access macros */
#if defined(CONFIG_8xx)
/* for a 8xx __raw_xxx's are sufficient */
#define __fec_out32(addr, x) __raw_writel(x, addr)
#define __fec_out16(addr, x) __raw_writew(x, addr)
#define __fec_in32(addr) __raw_readl(addr)
#define __fec_in16(addr) __raw_readw(addr)
#else
/* for others play it safe */
#define __fec_out32(addr, x) out_be32(addr, x)
#define __fec_out16(addr, x) out_be16(addr, x)
#define __fec_in32(addr) in_be32(addr)
#define __fec_in16(addr) in_be16(addr)
#endif
/* write */
#define FW(_fecp, _reg, _v) __fec_out32(&(_fecp)->fec_ ## _reg, (_v))
/* read */
#define FR(_fecp, _reg) __fec_in32(&(_fecp)->fec_ ## _reg)
/* set bits */
#define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
/* clear bits */
#define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
/* buffer descriptor access macros */
/* write */
#define CBDW_SC(_cbd, _sc) __fec_out16(&(_cbd)->cbd_sc, (_sc))
#define CBDW_DATLEN(_cbd, _datlen) __fec_out16(&(_cbd)->cbd_datlen, (_datlen))
#define CBDW_BUFADDR(_cbd, _bufaddr) __fec_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
/* read */
#define CBDR_SC(_cbd) __fec_in16(&(_cbd)->cbd_sc)
#define CBDR_DATLEN(_cbd) __fec_in16(&(_cbd)->cbd_datlen)
#define CBDR_BUFADDR(_cbd) __fec_in32(&(_cbd)->cbd_bufaddr)
/* set bits */
#define CBDS_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))
/* clear bits */
#define CBDC_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
/***************************************************************************/
#endif
drivers/net/fec_8xx/fec_main.c 已删除 100644 → 0
浏览文件 @ bfd123bf
此差异已折叠。
drivers/net/fec_8xx/fec_mii.c 已删除 100644 → 0
浏览文件 @ bfd123bf
/*
* Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
*
* Copyright (c) 2003 Intracom S.A.
* by Pantelis Antoniou <panto@intracom.gr>
*
* Heavily based on original FEC driver by Dan Malek <dan@embeddededge.com>
* and modifications by Joakim Tjernlund <joakim.tjernlund@lumentis.se>
*
* Released under the GPL
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/bitops.h>
#include <asm/8xx_immap.h>
#include <asm/pgtable.h>
#include <asm/mpc8xx.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/cpm1.h>
/*************************************************/
#include "fec_8xx.h"
/*************************************************/
/* Make MII read/write commands for the FEC.
*/
#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
#define mk_mii_end 0
/*************************************************/
/* XXX both FECs use the MII interface of FEC1 */
static DEFINE_SPINLOCK(fec_mii_lock);
#define FEC_MII_LOOPS 10000
int fec_mii_read(struct net_device *dev, int phy_id, int location)
{
struct fec_enet_private *fep = netdev_priv(dev);
fec_t *fecp;
int i, ret = -1;
unsigned long flags;
/* XXX MII interface is only connected to FEC1 */
fecp = &((immap_t *) IMAP_ADDR)->im_cpm.cp_fec;
spin_lock_irqsave(&fec_mii_lock, flags);
if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0) {
FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
FW(fecp, ievent, FEC_ENET_MII);
}
/* Add PHY address to register command. */
FW(fecp, mii_speed, fep->fec_phy_speed);
FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
for (i = 0; i < FEC_MII_LOOPS; i++)
if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
break;
if (i < FEC_MII_LOOPS) {
FW(fecp, ievent, FEC_ENET_MII);
ret = FR(fecp, mii_data) & 0xffff;
}
spin_unlock_irqrestore(&fec_mii_lock, flags);
return ret;
}
void fec_mii_write(struct net_device *dev, int phy_id, int location, int value)
{
struct fec_enet_private *fep = netdev_priv(dev);
fec_t *fecp;
unsigned long flags;
int i;
/* XXX MII interface is only connected to FEC1 */
fecp = &((immap_t *) IMAP_ADDR)->im_cpm.cp_fec;
spin_lock_irqsave(&fec_mii_lock, flags);
if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0) {
FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
FW(fecp, ievent, FEC_ENET_MII);
}
/* Add PHY address to register command. */
FW(fecp, mii_speed, fep->fec_phy_speed); /* always adapt mii speed */
FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
for (i = 0; i < FEC_MII_LOOPS; i++)
if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
break;
if (i < FEC_MII_LOOPS)
FW(fecp, ievent, FEC_ENET_MII);
spin_unlock_irqrestore(&fec_mii_lock, flags);
}
/*************************************************/
#ifdef CONFIG_FEC_8XX_GENERIC_PHY
/*
* Generic PHY support.
* Should work for all PHYs, but link change is detected by polling
*/
static void generic_timer_callback(unsigned long data)
{
struct net_device *dev = (struct net_device *)data;
struct fec_enet_private *fep = netdev_priv(dev);
fep->phy_timer_list.expires = jiffies + HZ / 2;
add_timer(&fep->phy_timer_list);
fec_mii_link_status_change_check(dev, 0);
}
static void generic_startup(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
fep->phy_timer_list.expires = jiffies + HZ / 2; /* every 500ms */
fep->phy_timer_list.data = (unsigned long)dev;
fep->phy_timer_list.function = generic_timer_callback;
add_timer(&fep->phy_timer_list);
}
static void generic_shutdown(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
del_timer_sync(&fep->phy_timer_list);
}
#endif
#ifdef CONFIG_FEC_8XX_DM9161_PHY
/* ------------------------------------------------------------------------- */
/* The Davicom DM9161 is used on the NETTA board */
/* register definitions */
#define MII_DM9161_ACR 16 /* Aux. Config Register */
#define MII_DM9161_ACSR 17 /* Aux. Config/Status Register */
#define MII_DM9161_10TCSR 18 /* 10BaseT Config/Status Reg. */
#define MII_DM9161_INTR 21 /* Interrupt Register */
#define MII_DM9161_RECR 22 /* Receive Error Counter Reg. */
#define MII_DM9161_DISCR 23 /* Disconnect Counter Register */
static void dm9161_startup(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
fec_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0000);
}
static void dm9161_ack_int(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
fec_mii_read(dev, fep->mii_if.phy_id, MII_DM9161_INTR);
}
static void dm9161_shutdown(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
fec_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0f00);
}
#endif
#ifdef CONFIG_FEC_8XX_LXT971_PHY
/* Support for LXT971/972 PHY */
#define MII_LXT971_PCR 16 /* Port Control Register */
#define MII_LXT971_SR2 17 /* Status Register 2 */
#define MII_LXT971_IER 18 /* Interrupt Enable Register */
#define MII_LXT971_ISR 19 /* Interrupt Status Register */
#define MII_LXT971_LCR 20 /* LED Control Register */
#define MII_LXT971_TCR 30 /* Transmit Control Register */
static void lxt971_startup(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x00F2);
}
static void lxt971_ack_int(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
fec_mii_read(dev, fep->mii_if.phy_id, MII_LXT971_ISR);
}
static void lxt971_shutdown(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x0000);
}
#endif
/**********************************************************************************/
static const struct phy_info phy_info[] = {
#ifdef CONFIG_FEC_8XX_DM9161_PHY
{
.id = 0x00181b88,
.name = "DM9161",
.startup = dm9161_startup,
.ack_int = dm9161_ack_int,
.shutdown = dm9161_shutdown,
},
#endif
#ifdef CONFIG_FEC_8XX_LXT971_PHY
{
.id = 0x0001378e,
.name = "LXT971/972",
.startup = lxt971_startup,
.ack_int = lxt971_ack_int,
.shutdown = lxt971_shutdown,
},
#endif
#ifdef CONFIG_FEC_8XX_GENERIC_PHY
{
.id = 0,
.name = "GENERIC",
.startup = generic_startup,
.shutdown = generic_shutdown,
},
#endif
};
/**********************************************************************************/
int fec_mii_phy_id_detect(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
const struct fec_platform_info *fpi = fep->fpi;
int i, r, start, end, phytype, physubtype;
const struct phy_info *phy;
int phy_hwid, phy_id;
/* if no MDIO */
if (fpi->use_mdio == 0)
return -1;
phy_hwid = -1;
fep->phy = NULL;
/* auto-detect? */
if (fpi->phy_addr == -1) {
start = 0;
end = 32;
} else { /* direct */
start = fpi->phy_addr;
end = start + 1;
}
for (phy_id = start; phy_id < end; phy_id++) {
r = fec_mii_read(dev, phy_id, MII_PHYSID1);
if (r == -1 || (phytype = (r & 0xffff)) == 0xffff)
continue;
r = fec_mii_read(dev, phy_id, MII_PHYSID2);
if (r == -1 || (physubtype = (r & 0xffff)) == 0xffff)
continue;
phy_hwid = (phytype << 16) | physubtype;
if (phy_hwid != -1)
break;
}
if (phy_hwid == -1) {
printk(KERN_ERR DRV_MODULE_NAME
": %s No PHY detected!\n", dev->name);
return -1;
}
for (i = 0, phy = phy_info; i < ARRAY_SIZE(phy_info); i++, phy++)
if (phy->id == (phy_hwid >> 4) || phy->id == 0)
break;
if (i >= ARRAY_SIZE(phy_info)) {
printk(KERN_ERR DRV_MODULE_NAME
": %s PHY id 0x%08x is not supported!\n",
dev->name, phy_hwid);
return -1;
}
fep->phy = phy;
printk(KERN_INFO DRV_MODULE_NAME
": %s Phy @ 0x%x, type %s (0x%08x)\n",
dev->name, phy_id, fep->phy->name, phy_hwid);
return phy_id;
}
void fec_mii_startup(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
const struct fec_platform_info *fpi = fep->fpi;
if (!fpi->use_mdio || fep->phy == NULL)
return;
if (fep->phy->startup == NULL)
return;
(*fep->phy->startup) (dev);
}
void fec_mii_shutdown(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
const struct fec_platform_info *fpi = fep->fpi;
if (!fpi->use_mdio || fep->phy == NULL)
return;
if (fep->phy->shutdown == NULL)
return;
(*fep->phy->shutdown) (dev);
}
void fec_mii_ack_int(struct net_device *dev)
{
struct fec_enet_private *fep = netdev_priv(dev);
const struct fec_platform_info *fpi = fep->fpi;
if (!fpi->use_mdio || fep->phy == NULL)
return;
if (fep->phy->ack_int == NULL)
return;
(*fep->phy->ack_int) (dev);
}
/* helper function */
static int mii_negotiated(struct mii_if_info *mii)
{
int advert, lpa, val;
if (!mii_link_ok(mii))
return 0;
val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR);
if ((val & BMSR_ANEGCOMPLETE) == 0)
return 0;
advert = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_ADVERTISE);
lpa = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_LPA);
return mii_nway_result(advert & lpa);
}
void fec_mii_link_status_change_check(struct net_device *dev, int init_media)
{
struct fec_enet_private *fep = netdev_priv(dev);
unsigned int media;
unsigned long flags;
if (mii_check_media(&fep->mii_if, netif_msg_link(fep), init_media) == 0)
return;
media = mii_negotiated(&fep->mii_if);
if (netif_carrier_ok(dev)) {
spin_lock_irqsave(&fep->lock, flags);
fec_restart(dev, !!(media & ADVERTISE_FULL),
(media & (ADVERTISE_100FULL | ADVERTISE_100HALF)) ?
100 : 10);
spin_unlock_irqrestore(&fep->lock, flags);
netif_start_queue(dev);
} else {
netif_stop_queue(dev);
spin_lock_irqsave(&fep->lock, flags);
fec_stop(dev);
spin_unlock_irqrestore(&fep->lock, flags);
}
}
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