提交 4b3d4d3d 编写于 作者: A Arnd Bergmann

Merge branch 'at91/cleanup' into next/drivers

This resolves some of the obvious conflicts between the at91 cleanup and
drivers branches.

Conflicts:
	arch/arm/mach-at91/at91sam9g45.c
	arch/arm/mach-at91/at91sam9rl.c
	drivers/rtc/Kconfig
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91SAM9G45=y
CONFIG_MACH_AT91SAM9M10G45EK=y
CONFIG_MACH_AT91SAM9_DT=y
CONFIG_AT91_SLOW_CLOCK=y
CONFIG_AEABI=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x71100000,25165824 root=/dev/ram0 rw"
CONFIG_AUTO_ZRELADDR=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
CONFIG_IPV6_SIT_6RD=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_ATMEL_TCLIB=y
CONFIG_ATMEL_SSC=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_MACB=y
CONFIG_DAVICOM_PHY=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_QT1070=y
CONFIG_KEYBOARD_QT2160=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_ATMEL=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_RESET=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91SAM9X_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_ATMEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_ATMEL_LCDC=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_ATMEL_AC97C=y
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ATMEL_USBA=y
CONFIG_USB_G_MULTI=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_MMC=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_ATMELMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_DMADEVICES=y
CONFIG_AT_HDMAC=y
CONFIG_DMATEST=m
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_IIO=y
CONFIG_AT91_ADC=y
CONFIG_PWM=y
CONFIG_PWM_ATMEL=y
CONFIG_EXT4_FS=y
CONFIG_FANOTIFY=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
# CONFIG_CRYPTO_HW is not set
CONFIG_FONTS=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91SAM9RL=y
CONFIG_MACH_AT91SAM9RLEK=y
# CONFIG_ARM_THUMB is not set
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,17105363 root=/dev/ram0 rw"
CONFIG_AUTO_ZRELADDR=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=24576
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_ATMEL=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_RESET=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91SAM9X_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_ATMEL=y
CONFIG_USB_GADGET=y
CONFIG_USB_ATMEL_USBA=y
CONFIG_MMC=y
CONFIG_MMC_ATMELMCI=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_IIO=y
CONFIG_AT91_ADC=y
CONFIG_PWM=y
CONFIG_PWM_ATMEL=y
CONFIG_EXT4_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
CONFIG_CRAMFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_UTF8=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_EXPERIMENTAL=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EMBEDDED=y
# CONFIG_HOTPLUG is not set
# CONFIG_ELF_CORE is not set
# CONFIG_FUTEX is not set
# CONFIG_TIMERFD is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_MMU is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91X40=y
CONFIG_MACH_AT91EB01=y
CONFIG_AT91_EARLY_USART0=y
CONFIG_CPU_ARM7TDMI=y
CONFIG_SET_MEM_PARAM=y
CONFIG_DRAM_BASE=0x01000000
CONFIG_DRAM_SIZE=0x00400000
CONFIG_FLASH_MEM_BASE=0x01400000
CONFIG_PROCESSOR_ID=0x14000040
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_BINFMT_FLAT=y
# CONFIG_SUSPEND is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y
CONFIG_BLK_DEV_RAM=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_ROMFS_FS=y
# CONFIG_ENABLE_MUST_CHECK is not set
...@@ -18,18 +18,14 @@ config HAVE_AT91_DBGU2 ...@@ -18,18 +18,14 @@ config HAVE_AT91_DBGU2
config AT91_USE_OLD_CLK config AT91_USE_OLD_CLK
bool bool
config AT91_PMC_UNIT
bool
default !ARCH_AT91X40
config COMMON_CLK_AT91 config COMMON_CLK_AT91
bool bool
default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK default USE_OF && !AT91_USE_OLD_CLK
select COMMON_CLK select COMMON_CLK
config OLD_CLK_AT91 config OLD_CLK_AT91
bool bool
default AT91_PMC_UNIT && AT91_USE_OLD_CLK default AT91_USE_OLD_CLK
config OLD_IRQ_AT91 config OLD_IRQ_AT91
bool bool
...@@ -65,16 +61,6 @@ choice ...@@ -65,16 +61,6 @@ choice
prompt "Core type" prompt "Core type"
config ARCH_AT91X40
bool "ARM7 AT91X40"
depends on !MMU
select CPU_ARM7TDMI
select ARCH_USES_GETTIMEOFFSET
select OLD_IRQ_AT91
help
Select this if you are using one of Atmel's AT91X40 SoC.
config SOC_SAM_V4_V5 config SOC_SAM_V4_V5
bool "ARM9 AT91SAM9/AT91RM9200" bool "ARM9 AT91SAM9/AT91RM9200"
help help
...@@ -199,7 +185,7 @@ config SOC_AT91SAM9N12 ...@@ -199,7 +185,7 @@ config SOC_AT91SAM9N12
endif # SOC_SAM_V4_V5 endif # SOC_SAM_V4_V5
if SOC_SAM_V4_V5 || ARCH_AT91X40 if SOC_SAM_V4_V5
source arch/arm/mach-at91/Kconfig.non_dt source arch/arm/mach-at91/Kconfig.non_dt
endif endif
......
...@@ -5,7 +5,6 @@ config HAVE_AT91_DATAFLASH_CARD ...@@ -5,7 +5,6 @@ config HAVE_AT91_DATAFLASH_CARD
choice choice
prompt "Atmel AT91 Processor Devices for non DT boards" prompt "Atmel AT91 Processor Devices for non DT boards"
depends on !ARCH_AT91X40
config ARCH_AT91_NONE config ARCH_AT91_NONE
bool "None" bool "None"
...@@ -34,18 +33,6 @@ config ARCH_AT91SAM9263 ...@@ -34,18 +33,6 @@ config ARCH_AT91SAM9263
select AT91_USE_OLD_CLK select AT91_USE_OLD_CLK
select OLD_IRQ_AT91 select OLD_IRQ_AT91
config ARCH_AT91SAM9RL
bool "AT91SAM9RL"
select SOC_AT91SAM9RL
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
config ARCH_AT91SAM9G45
bool "AT91SAM9G45"
select SOC_AT91SAM9G45
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
endchoice endchoice
config ARCH_AT91SAM9G20 config ARCH_AT91SAM9G20
...@@ -288,51 +275,6 @@ endif ...@@ -288,51 +275,6 @@ endif
# ---------------------------------------------------------- # ----------------------------------------------------------
if ARCH_AT91SAM9RL
comment "AT91SAM9RL Board Type"
config MACH_AT91SAM9RLEK
bool "Atmel AT91SAM9RL-EK Evaluation Kit"
help
Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
endif
# ----------------------------------------------------------
if ARCH_AT91SAM9G45
comment "AT91SAM9G45 Board Type"
config MACH_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
help
Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
<http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
endif
# ----------------------------------------------------------
if ARCH_AT91X40
comment "AT91X40 Board Type"
config MACH_AT91EB01
bool "Atmel AT91EB01 Evaluation Kit"
help
Select this if you are using Atmel's AT91EB01 Evaluation Kit.
It is also a popular target for simulators such as GDB's
ARM simulator (commonly known as the ARMulator) and the
Skyeye simulator.
endif
# ----------------------------------------------------------
comment "AT91 Board Options" comment "AT91 Board Options"
config MTD_AT91_DATAFLASH_CARD config MTD_AT91_DATAFLASH_CARD
......
...@@ -24,9 +24,6 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o ...@@ -24,9 +24,6 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
# AT91RM9200 board-specific support # AT91RM9200 board-specific support
obj-$(CONFIG_MACH_ONEARM) += board-1arm.o obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
...@@ -58,9 +55,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o ...@@ -58,9 +55,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
# AT91SAM9263 board-specific support # AT91SAM9263 board-specific support
obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
# AT91SAM9RL board-specific support
obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
# AT91SAM9G20 board-specific support # AT91SAM9G20 board-specific support
obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
...@@ -72,9 +66,6 @@ obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o ...@@ -72,9 +66,6 @@ obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o
# AT91SAM9260/AT91SAM9G20 board-specific support # AT91SAM9260/AT91SAM9G20 board-specific support
obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
# AT91SAM9G45 board-specific support
obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
# AT91SAM board with device-tree # AT91SAM board with device-tree
obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
...@@ -82,9 +73,6 @@ obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o ...@@ -82,9 +73,6 @@ obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
# SAMA5 board with device-tree # SAMA5 board with device-tree
obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o
# AT91X40 board-specific support
obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
# Drivers # Drivers
obj-y += leds.o obj-y += leds.o
......
...@@ -10,358 +10,12 @@ ...@@ -10,358 +10,12 @@
* *
*/ */
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/clk/at91_pmc.h>
#include <linux/platform_device.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h> #include <asm/system_misc.h>
#include <mach/at91sam9g45.h>
#include <mach/cpu.h> #include <mach/cpu.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include "at91_aic.h"
#include "soc.h" #include "soc.h"
#include "generic.h" #include "generic.h"
#include "sam9_smc.h"
#include "pm.h"
#if defined(CONFIG_OLD_CLK_AT91)
#include "clock.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
.name = "pioC_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioDE_clk = {
.name = "pioDE_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk trng_clk = {
.name = "trng_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
.name = "usart3_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_US3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
.name = "twi0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
.name = "twi1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
.name = "ssc0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
.name = "ssc1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb0_clk = {
.name = "tcb0_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
.name = "pwm_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
.name = "tsc_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_TSC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
.name = "dma_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_DMA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uhphs_clk = {
.name = "uhphs_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
.name = "ac97_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
.name = "pclk",
.pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
.name = "udphs_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
.name = "mci1_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
.type = CLK_TYPE_PERIPHERAL,
};
/* Video decoder clock - Only for sam9m10/sam9m11 */
static struct clk vdec_clk = {
.name = "vdec_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_op_clk = {
.name = "adc_op_clk",
.type = CLK_TYPE_PERIPHERAL,
.rate_hz = 300000,
};
/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
static struct clk aestdessha_clk = {
.name = "aestdessha_clk",
.pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
&pioC_clk,
&pioDE_clk,
&trng_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&usart3_clk,
&mmc0_clk,
&twi0_clk,
&twi1_clk,
&spi0_clk,
&spi1_clk,
&ssc0_clk,
&ssc1_clk,
&tcb0_clk,
&pwm_clk,
&tsc_clk,
&dma_clk,
&uhphs_clk,
&lcdc_clk,
&ac97_clk,
&macb_clk,
&isi_clk,
&udphs_clk,
&mmc1_clk,
&adc_op_clk,
&aestdessha_clk,
// irq0
};
static struct clk_lookup periph_clocks_lookups[] = {
/* One additional fake clock for macb_hclk */
CLKDEV_CON_ID("hclk", &macb_clk),
/* One additional fake clock for ohci */
CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.0", &clk32k),
/* more usart lookup table for DT entries */
CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
/* more tc lookup table for DT entries */
CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
CLKDEV_CON_DEV_ID(NULL, "fffffd20.rtc", &clk32k),
CLKDEV_CON_ID("pioA", &pioA_clk),
CLKDEV_CON_ID("pioB", &pioB_clk),
CLKDEV_CON_ID("pioC", &pioC_clk),
CLKDEV_CON_ID("pioD", &pioDE_clk),
CLKDEV_CON_ID("pioE", &pioDE_clk),
/* Fake adc clock */
CLKDEV_CON_ID("adc_clk", &tsc_clk),
CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static void __init at91sam9g45_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clkdev_add_table(periph_clocks_lookups,
ARRAY_SIZE(periph_clocks_lookups));
clkdev_add_table(usart_clocks_lookups,
ARRAY_SIZE(usart_clocks_lookups));
if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
clk_register(&vdec_clk);
clk_register(&pck0);
clk_register(&pck1);
}
#else
#define at91sam9g45_register_clocks NULL
#endif
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
{
.id = AT91SAM9G45_ID_PIOA,
.regbase = AT91SAM9G45_BASE_PIOA,
}, {
.id = AT91SAM9G45_ID_PIOB,
.regbase = AT91SAM9G45_BASE_PIOB,
}, {
.id = AT91SAM9G45_ID_PIOC,
.regbase = AT91SAM9G45_BASE_PIOC,
}, {
.id = AT91SAM9G45_ID_PIODE,
.regbase = AT91SAM9G45_BASE_PIOD,
}, {
.id = AT91SAM9G45_ID_PIODE,
.regbase = AT91SAM9G45_BASE_PIOE,
}
};
/* -------------------------------------------------------------------- /* --------------------------------------------------------------------
* AT91SAM9G45 processor initialization * AT91SAM9G45 processor initialization
...@@ -372,113 +26,14 @@ static void __init at91sam9g45_map_io(void) ...@@ -372,113 +26,14 @@ static void __init at91sam9g45_map_io(void)
at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE); at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
} }
static void __init at91sam9g45_ioremap_registers(void)
{
at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
at91_pm_set_standby(at91_ddr_standby);
}
static void __init at91sam9g45_initialize(void) static void __init at91sam9g45_initialize(void)
{ {
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC); at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT); at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
/* Register GPIO subsystem */
at91_gpio_init(at91sam9g45_gpio, 5);
}
static struct resource rstc_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_RSTC,
.end = AT91SAM9G45_BASE_RSTC + SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9G45_BASE_DDRSDRC1,
.end = AT91SAM9G45_BASE_DDRSDRC1 + SZ_512 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = AT91SAM9G45_BASE_DDRSDRC0,
.end = AT91SAM9G45_BASE_DDRSDRC0 + SZ_512 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device rstc_device = {
.name = "at91-sam9g45-reset",
.resource = rstc_resources,
.num_resources = ARRAY_SIZE(rstc_resources),
};
static struct resource shdwc_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_SHDWC,
.end = AT91SAM9G45_BASE_SHDWC + SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device shdwc_device = {
.name = "at91-poweroff",
.resource = shdwc_resources,
.num_resources = ARRAY_SIZE(shdwc_resources),
};
static void __init at91sam9g45_register_devices(void)
{
platform_device_register(&rstc_device);
platform_device_register(&shdwc_device);
} }
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller (FIQ) */
7, /* System Peripherals */
1, /* Parallel IO Controller A */
1, /* Parallel IO Controller B */
1, /* Parallel IO Controller C */
1, /* Parallel IO Controller D and E */
0,
5, /* USART 0 */
5, /* USART 1 */
5, /* USART 2 */
5, /* USART 3 */
0, /* Multimedia Card Interface 0 */
6, /* Two-Wire Interface 0 */
6, /* Two-Wire Interface 1 */
5, /* Serial Peripheral Interface 0 */
5, /* Serial Peripheral Interface 1 */
4, /* Serial Synchronous Controller 0 */
4, /* Serial Synchronous Controller 1 */
0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
0, /* Pulse Width Modulation Controller */
0, /* Touch Screen Controller */
0, /* DMA Controller */
2, /* USB Host High Speed port */
3, /* LDC Controller */
5, /* AC97 Controller */
3, /* Ethernet */
0, /* Image Sensor Interface */
2, /* USB Device High speed port */
0, /* AESTDESSHA Crypto HW Accelerators */
0, /* Multimedia Card Interface 1 */
0,
0, /* Advanced Interrupt Controller (IRQ0) */
};
static void __init at91sam9g45_init_time(void) static void __init at91sam9g45_init_time(void)
{ {
at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS); at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
...@@ -486,11 +41,6 @@ static void __init at91sam9g45_init_time(void) ...@@ -486,11 +41,6 @@ static void __init at91sam9g45_init_time(void)
AT91_SOC_START(at91sam9g45) AT91_SOC_START(at91sam9g45)
.map_io = at91sam9g45_map_io, .map_io = at91sam9g45_map_io,
.default_irq_priority = at91sam9g45_default_irq_priority,
.extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
.ioremap_registers = at91sam9g45_ioremap_registers,
.register_clocks = at91sam9g45_register_clocks,
.register_devices = at91sam9g45_register_devices,
.init = at91sam9g45_initialize, .init = at91sam9g45_initialize,
.init_time = at91sam9g45_init_time, .init_time = at91sam9g45_init_time,
AT91_SOC_END AT91_SOC_END
此差异已折叠。
...@@ -9,286 +9,13 @@ ...@@ -9,286 +9,13 @@
* more details. * more details.
*/ */
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk/at91_pmc.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h> #include <asm/system_misc.h>
#include <mach/cpu.h> #include <mach/cpu.h>
#include <mach/at91_dbgu.h> #include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include "at91_aic.h"
#include "soc.h" #include "soc.h"
#include "generic.h" #include "generic.h"
#include "sam9_smc.h"
#include "pm.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
#if defined(CONFIG_OLD_CLK_AT91)
#include "clock.h"
/*
* The peripheral clocks.
*/
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
.name = "pioC_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioD_clk = {
.name = "pioD_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
.name = "usart3_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_US3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
.name = "mci_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_MCI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
.name = "twi0_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
.name = "twi1_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi_clk = {
.name = "spi_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_SPI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
.name = "ssc0_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
.name = "ssc1_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
.name = "tc0_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_TC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
.name = "tc1_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_TC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
.name = "tc2_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
.name = "pwm_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
.name = "tsc_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_TSC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
.name = "dma_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_DMA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
.name = "udphs_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
.name = "ac97_clk",
.pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_op_clk = {
.name = "adc_op_clk",
.type = CLK_TYPE_PERIPHERAL,
.rate_hz = 1000000,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
&pioC_clk,
&pioD_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&usart3_clk,
&mmc_clk,
&twi0_clk,
&twi1_clk,
&spi_clk,
&ssc0_clk,
&ssc1_clk,
&tc0_clk,
&tc1_clk,
&tc2_clk,
&pwm_clk,
&tsc_clk,
&dma_clk,
&udphs_clk,
&lcdc_clk,
&ac97_clk,
&adc_op_clk,
// irq0
};
static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
CLKDEV_CON_ID("pioA", &pioA_clk),
CLKDEV_CON_ID("pioB", &pioB_clk),
CLKDEV_CON_ID("pioC", &pioC_clk),
CLKDEV_CON_ID("pioD", &pioD_clk),
CLKDEV_CON_DEV_ID(NULL, "rtc-at91sam9.0", &clk32k),
/* more lookup table for DT entries */
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
CLKDEV_CON_DEV_ID(NULL, "fffffd20.rtc", &clk32k),
CLKDEV_CON_ID("adc_clk", &tsc_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static void __init at91sam9rl_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clkdev_add_table(periph_clocks_lookups,
ARRAY_SIZE(periph_clocks_lookups));
clkdev_add_table(usart_clocks_lookups,
ARRAY_SIZE(usart_clocks_lookups));
clk_register(&pck0);
clk_register(&pck1);
}
#endif
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
{
.id = AT91SAM9RL_ID_PIOA,
.regbase = AT91SAM9RL_BASE_PIOA,
}, {
.id = AT91SAM9RL_ID_PIOB,
.regbase = AT91SAM9RL_BASE_PIOB,
}, {
.id = AT91SAM9RL_ID_PIOC,
.regbase = AT91SAM9RL_BASE_PIOC,
}, {
.id = AT91SAM9RL_ID_PIOD,
.regbase = AT91SAM9RL_BASE_PIOD,
}
};
/* -------------------------------------------------------------------- /* --------------------------------------------------------------------
* AT91SAM9RL processor initialization * AT91SAM9RL processor initialization
...@@ -311,107 +38,14 @@ static void __init at91sam9rl_map_io(void) ...@@ -311,107 +38,14 @@ static void __init at91sam9rl_map_io(void)
at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size); at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
} }
static void __init at91sam9rl_ioremap_registers(void)
{
at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
at91_pm_set_standby(at91sam9_sdram_standby);
}
static void __init at91sam9rl_initialize(void) static void __init at91sam9rl_initialize(void)
{ {
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC); at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT); at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
/* Register GPIO subsystem */
at91_gpio_init(at91sam9rl_gpio, 4);
}
static struct resource rstc_resources[] = {
[0] = {
.start = AT91SAM9RL_BASE_RSTC,
.end = AT91SAM9RL_BASE_RSTC + SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9RL_BASE_SDRAMC,
.end = AT91SAM9RL_BASE_SDRAMC + SZ_512 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device rstc_device = {
.name = "at91-sam9260-reset",
.resource = rstc_resources,
.num_resources = ARRAY_SIZE(rstc_resources),
};
static struct resource shdwc_resources[] = {
[0] = {
.start = AT91SAM9RL_BASE_SHDWC,
.end = AT91SAM9RL_BASE_SHDWC + SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device shdwc_device = {
.name = "at91-poweroff",
.resource = shdwc_resources,
.num_resources = ARRAY_SIZE(shdwc_resources),
};
static void __init at91sam9rl_register_devices(void)
{
platform_device_register(&rstc_device);
platform_device_register(&shdwc_device);
} }
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller */
7, /* System Peripherals */
1, /* Parallel IO Controller A */
1, /* Parallel IO Controller B */
1, /* Parallel IO Controller C */
1, /* Parallel IO Controller D */
5, /* USART 0 */
5, /* USART 1 */
5, /* USART 2 */
5, /* USART 3 */
0, /* Multimedia Card Interface */
6, /* Two-Wire Interface 0 */
6, /* Two-Wire Interface 1 */
5, /* Serial Peripheral Interface */
4, /* Serial Synchronous Controller 0 */
4, /* Serial Synchronous Controller 1 */
0, /* Timer Counter 0 */
0, /* Timer Counter 1 */
0, /* Timer Counter 2 */
0,
0, /* Touch Screen Controller */
0, /* DMA Controller */
2, /* USB Device High speed port */
2, /* LCD Controller */
6, /* AC97 Controller */
0,
0,
0,
0,
0,
0,
0, /* Advanced Interrupt Controller */
};
static void __init at91sam9rl_init_time(void) static void __init at91sam9rl_init_time(void)
{ {
at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS); at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
...@@ -419,13 +53,6 @@ static void __init at91sam9rl_init_time(void) ...@@ -419,13 +53,6 @@ static void __init at91sam9rl_init_time(void)
AT91_SOC_START(at91sam9rl) AT91_SOC_START(at91sam9rl)
.map_io = at91sam9rl_map_io, .map_io = at91sam9rl_map_io,
.default_irq_priority = at91sam9rl_default_irq_priority,
.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
.ioremap_registers = at91sam9rl_ioremap_registers,
#if defined(CONFIG_OLD_CLK_AT91)
.register_clocks = at91sam9rl_register_clocks,
#endif
.register_devices = at91sam9rl_register_devices,
.init = at91sam9rl_initialize, .init = at91sam9rl_initialize,
.init_time = at91sam9rl_init_time, .init_time = at91sam9rl_init_time,
AT91_SOC_END AT91_SOC_END
此差异已折叠。
/*
* arch/arm/mach-at91/at91x40.c
*
* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
* Copyright (C) 2005 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/proc-fns.h>
#include <asm/system_misc.h>
#include <asm/mach/arch.h>
#include <mach/at91x40.h>
#include <mach/at91_st.h>
#include <mach/hardware.h>
#include "at91_aic.h"
#include "generic.h"
/*
* Export the clock functions for the AT91X40. Some external code common
* to all AT91 family parts relys on this, like the gpio and serial support.
*/
int clk_enable(struct clk *clk)
{
return 0;
}
void clk_disable(struct clk *clk)
{
}
unsigned long clk_get_rate(struct clk *clk)
{
return AT91X40_MASTER_CLOCK;
}
static void at91x40_idle(void)
{
/*
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
__raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
cpu_do_idle();
}
void __init at91x40_initialize(unsigned long main_clock)
{
arm_pm_idle = at91x40_idle;
}
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller (FIQ) */
0, /* System Peripherals */
0, /* USART 0 */
0, /* USART 1 */
2, /* Timer Counter 0 */
2, /* Timer Counter 1 */
2, /* Timer Counter 2 */
0, /* Watchdog timer */
0, /* Parallel IO Controller A */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* External IRQ0 */
0, /* External IRQ1 */
0, /* External IRQ2 */
};
void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
u32 extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
| (1 << AT91X40_ID_IRQ2);
if (!priority)
priority = at91x40_default_irq_priority;
at91_aic_init(priority, extern_irq);
}
/*
* arch/arm/mach-at91/at91x40_time.c
*
* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/at91x40.h>
#include <asm/mach/time.h>
#include "at91_tc.h"
#define at91_tc_read(field) \
__raw_readl(AT91_IO_P2V(AT91_TC) + field)
#define at91_tc_write(field, value) \
__raw_writel(value, AT91_IO_P2V(AT91_TC) + field)
/*
* 3 counter/timer units present.
*/
#define AT91_TC_CLK0BASE 0
#define AT91_TC_CLK1BASE 0x40
#define AT91_TC_CLK2BASE 0x80
static u32 at91x40_gettimeoffset(void)
{
return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 /
(AT91X40_MASTER_CLOCK / 128)) * 1000;
}
static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
{
at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
timer_tick();
return IRQ_HANDLED;
}
static struct irqaction at91x40_timer_irq = {
.name = "at91_tick",
.flags = IRQF_TIMER,
.handler = at91x40_timer_interrupt
};
void __init at91x40_timer_init(void)
{
unsigned int v;
arch_gettimeoffset = at91x40_gettimeoffset;
at91_tc_write(AT91_TC_BCR, 0);
v = at91_tc_read(AT91_TC_BMR);
v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
at91_tc_write(AT91_TC_BMR, v);
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
}
/*
* arch/arm/mach-at91/board-eb01.c
*
* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
static void __init at91eb01_init_irq(void)
{
at91x40_init_interrupts(NULL);
}
static void __init at91eb01_init_early(void)
{
at91x40_initialize(40000000);
}
MACHINE_START(AT91EB01, "Atmel AT91 EB01")
/* Maintainer: Greg Ungerer <gerg@snapgear.com> */
.init_time = at91x40_timer_init,
.handle_irq = at91_aic_handle_irq,
.init_early = at91eb01_init_early,
.init_irq = at91eb01_init_irq,
MACHINE_END
此差异已折叠。
此差异已折叠。
...@@ -24,14 +24,12 @@ extern void __init at91_init_sram(int bank, unsigned long base, ...@@ -24,14 +24,12 @@ extern void __init at91_init_sram(int bank, unsigned long base,
/* Processors */ /* Processors */
extern void __init at91rm9200_set_type(int type); extern void __init at91rm9200_set_type(int type);
extern void __init at91_initialize(unsigned long main_clock); extern void __init at91_initialize(unsigned long main_clock);
extern void __init at91x40_initialize(unsigned long main_clock);
extern void __init at91rm9200_dt_initialize(void); extern void __init at91rm9200_dt_initialize(void);
extern void __init at91_dt_initialize(void); extern void __init at91_dt_initialize(void);
/* Interrupts */ /* Interrupts */
extern void __init at91_init_irq_default(void); extern void __init at91_init_irq_default(void);
extern void __init at91_init_interrupts(unsigned int priority[]); extern void __init at91_init_interrupts(unsigned int priority[]);
extern void __init at91x40_init_interrupts(unsigned int priority[]);
extern void __init at91_aic_init(unsigned int priority[], extern void __init at91_aic_init(unsigned int priority[],
unsigned int ext_irq_mask); unsigned int ext_irq_mask);
extern int __init at91_aic_of_init(struct device_node *node, extern int __init at91_aic_of_init(struct device_node *node,
...@@ -50,7 +48,6 @@ extern void at91rm9200_ioremap_st(u32 addr); ...@@ -50,7 +48,6 @@ extern void at91rm9200_ioremap_st(u32 addr);
extern void at91rm9200_timer_init(void); extern void at91rm9200_timer_init(void);
extern void at91sam926x_ioremap_pit(u32 addr); extern void at91sam926x_ioremap_pit(u32 addr);
extern void at91sam926x_pit_init(int irq); extern void at91sam926x_pit_init(int irq);
extern void at91x40_timer_init(void);
/* Clocks */ /* Clocks */
#ifdef CONFIG_OLD_CLK_AT91 #ifdef CONFIG_OLD_CLK_AT91
......
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
#ifndef AT91_DBGU_H #ifndef AT91_DBGU_H
#define AT91_DBGU_H #define AT91_DBGU_H
#if !defined(CONFIG_ARCH_AT91X40)
#define AT91_DBGU_CR (0x00) /* Control Register */ #define AT91_DBGU_CR (0x00) /* Control Register */
#define AT91_DBGU_MR (0x04) /* Mode Register */ #define AT91_DBGU_MR (0x04) /* Mode Register */
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ #define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
...@@ -34,8 +33,6 @@ ...@@ -34,8 +33,6 @@
#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ #define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
#endif /* AT91_DBGU */
/* /*
* Some AT91 parts that don't have full DEBUG units still support the ID * Some AT91 parts that don't have full DEBUG units still support the ID
* and extensions register. * and extensions register.
......
/*
* arch/arm/mach-at91/include/mach/at91x40.h
*
* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91X40_H
#define AT91X40_H
/*
* IRQ list.
*/
#define AT91X40_ID_USART0 2 /* USART port 0 */
#define AT91X40_ID_USART1 3 /* USART port 1 */
#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */
#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/
#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/
#define AT91X40_ID_WD 7 /* Watchdog? */
#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */
#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */
#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */
#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
/*
* System Peripherals
*/
#define AT91_BASE_SYS 0xffc00000
#define AT91_EBI 0xffe00000 /* External Bus Interface */
#define AT91_SF 0xfff00000 /* Special Function */
#define AT91_USART1 0xfffcc000 /* USART 1 */
#define AT91_USART0 0xfffd0000 /* USART 0 */
#define AT91_TC 0xfffe0000 /* Timer Counter */
#define AT91_PIOA 0xffff0000 /* PIO Controller A */
#define AT91_PS 0xffff4000 /* Power Save */
#define AT91_WD 0xffff8000 /* Watchdog Timer */
/*
* The AT91x40 series doesn't have a debug unit like the other AT91 parts.
* But it does have a chip identify register and extension ID, so define at
* least these here.
*/
#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
/*
* Support defines for the simple Power Controller module.
*/
#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */
#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */
#define AT91X40_MASTER_CLOCK 40000000
#endif /* AT91X40_H */
...@@ -62,7 +62,6 @@ ...@@ -62,7 +62,6 @@
#define ARCH_EXID_SAMA5D43 0x00000003 #define ARCH_EXID_SAMA5D43 0x00000003
#define ARCH_EXID_SAMA5D44 0x00000004 #define ARCH_EXID_SAMA5D44 0x00000004
#define ARCH_FAMILY_AT91X92 0x09200000
#define ARCH_FAMILY_AT91SAM9 0x01900000 #define ARCH_FAMILY_AT91SAM9 0x01900000
#define ARCH_FAMILY_AT91SAM9XE 0x02900000 #define ARCH_FAMILY_AT91SAM9XE 0x02900000
......
...@@ -24,9 +24,6 @@ ...@@ -24,9 +24,6 @@
/* sama5d4 */ /* sama5d4 */
#define AT91_BASE_DBGU2 0xfc069000 #define AT91_BASE_DBGU2 0xfc069000
#if defined(CONFIG_ARCH_AT91X40)
#include <mach/at91x40.h>
#else
#include <mach/at91rm9200.h> #include <mach/at91rm9200.h>
#include <mach/at91sam9260.h> #include <mach/at91sam9260.h>
#include <mach/at91sam9261.h> #include <mach/at91sam9261.h>
...@@ -51,8 +48,6 @@ ...@@ -51,8 +48,6 @@
*/ */
#define AT91_BASE_SYS 0xffffc000 #define AT91_BASE_SYS 0xffffc000
#endif
/* /*
* On sama5d4 there is no system controller, we map some needed peripherals * On sama5d4 there is no system controller, we map some needed peripherals
*/ */
......
...@@ -31,7 +31,6 @@ ...@@ -31,7 +31,6 @@
void __iomem *at91_uart; void __iomem *at91_uart;
#if !defined(CONFIG_ARCH_AT91X40)
static const u32 uarts_rm9200[] = { static const u32 uarts_rm9200[] = {
AT91_BASE_DBGU0, AT91_BASE_DBGU0,
AT91RM9200_BASE_US0, AT91RM9200_BASE_US0,
...@@ -188,12 +187,6 @@ static inline void arch_decomp_setup(void) ...@@ -188,12 +187,6 @@ static inline void arch_decomp_setup(void)
at91_uart = NULL; at91_uart = NULL;
} }
#else
static inline void arch_decomp_setup(void)
{
at91_uart = NULL;
}
#endif
/* /*
* The following code assumes the serial port has already been * The following code assumes the serial port has already been
......
...@@ -418,7 +418,7 @@ void __init at91_ioremap_matrix(u32 base_addr) ...@@ -418,7 +418,7 @@ void __init at91_ioremap_matrix(u32 base_addr)
panic(pr_fmt("Impossible to ioremap at91_matrix_base\n")); panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
} }
#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40) #if defined(CONFIG_OF)
static struct of_device_id ramc_ids[] = { static struct of_device_id ramc_ids[] = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
......
...@@ -1110,7 +1110,7 @@ config RTC_DRV_AT91RM9200 ...@@ -1110,7 +1110,7 @@ config RTC_DRV_AT91RM9200
config RTC_DRV_AT91SAM9 config RTC_DRV_AT91SAM9
tristate "AT91SAM9 RTT as RTC" tristate "AT91SAM9 RTT as RTC"
depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40) depends on ARCH_AT91 && !ARCH_AT91RM9200
select MFD_SYSCON select MFD_SYSCON
help help
Some AT91SAM9 SoCs provide an RTT (Real Time Timer) block which Some AT91SAM9 SoCs provide an RTT (Real Time Timer) block which
......
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