提交 472c95a6 编写于 作者: A Andrzej Hajda 提交者: Kukjin Kim

dt-bindings: add asynchronous bridge clock for exynos

The patch adds bindings for clocks required by async-bridges
present in the particular power domain.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NKukjin Kim <kgene@kernel.org>
上级 46a0b9ff
...@@ -22,6 +22,9 @@ Optional Properties: ...@@ -22,6 +22,9 @@ Optional Properties:
- pclkN, clkN: Pairs of parent of input clock and input clock to the - pclkN, clkN: Pairs of parent of input clock and input clock to the
devices in this power domain. Maximum of 4 pairs (N = 0 to 3) devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
are supported currently. are supported currently.
- asbN: Clocks required by asynchronous bridges (ASB) present in
the power domain. These clock should be enabled during power
domain on/off operations.
Node of a device using power domains must have a power-domains property Node of a device using power domains must have a power-domains property
defined with a phandle to respective power domain. defined with a phandle to respective power domain.
......
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